MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 114

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Reset, Clocking, and Initialization
Figure 4-1
4.2.3
The HRESET signal is initiated externally by asserting HRESET or internally when the device detects a
reason to generate an internal hard reset sequence. In both cases, the device continues asserting HRESET
throughout the HRESET state. The hard reset sequence time varies according to the configuration source
and SYS_CLK_IN frequency. The reset configuration input signal (CFG_RESET_SOURCE) is not
sampled by hard reset (only by power-on reset), so the device immediately starts loading the reset
configuration words and configures the device as explained in
Configuration Words.”
signal and exits the HRESET state. An external pull-up resistor should negate the signals. After negation
is detected, a 16-cycle period is taken before testing for the presence of an external (hard) reset.
4-6
Reset Configuration
Reset Configuration
Words Loading
Input Signals
shows a timing diagram of the power-on reset flow.
SYS_CLK_IN
Hard Reset Flow
PORESET
HRESET
(Output)
It takes about 150 SYS_CLK_IN cycles between the negation of PORESET
and access to reset configuration word.
Because the device does not sample the reset configuration input signals
(CFG_RESET_SOURCE) during a hard reset flow, setting a new value on
those signals (other than that set during power-on reset) has no effect.
(Input)
(Input)
TRST
Min. 32 SYS_CLK_IN
After the configuration sequence completes, the device releases the HRESET
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Stable clock
cycles
Figure 4-1. Power-On Reset Flow
configuration words
Start loading reset
NOTE
NOTE
Section 4.3.3, “Loading the Reset
locked (no
indication)
PLLs are
external
Duration depends on
configuration words.
End loading reset
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