MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 287
MPC8308VMAGD
Manufacturer Part Number
MPC8308VMAGD
Description
MPU POWERQUICC II PRO 473MAPBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8308VMAGD.pdf
(90 pages)
2.MPC8308VMAGD.pdf
(2 pages)
3.MPC8308VMAGD.pdf
(1170 pages)
4.MPC8308VMAGD.pdf
(14 pages)
Specifications of MPC8308VMAGD
Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
400MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
473-MAPBGA
Product
Network Processor
Data Rate
256 bps
Frequency
400 MHz
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Supply Current (max)
5 uA
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
0 C
Interface
I2C, JTAG, SPI
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Table 8-10
8.5.4
SIPRR_A, shown in
receive request (TSEC1 Rx), TSEC1 transmit/receive error (TSEC1 Err), and internal interrupt signals.
For more information, see
Freescale Semiconductor
0–31 INT n Each implemented bit (listed in
Bits Name
defines the bit fields of SIPNR_L.
System Internal Interrupt Group A Priority Register (SIPRR_A)
received, the interrupt controller sets the corresponding SIPNR bit. When a pending interrupt is handled, the user
clears the SIPNR bit by clearing the corresponding event register bit.
SIPNR bits are read only. Writing to this register has no effect.
Note that the SIPNR bit positions are not changed according to their relative priority.
For unimplemented bits, writes are ignored, read = 0.
Table 8-9. SIPNR_L/SIFCR_L/SIMSR_L Bit Assignments (continued)
Figure
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Section 8.6.3, “Internal Interrupts Group Relative Priority.”
8-6, defines the priority between TSEC1 transmit request (TSEC1 Tx), TSEC1
Table 8-10. SIPNR_L Field Descriptions
Table
15–16
27–29
Bits
17
18
19
20
21
22
23
24
25
26
30
31
10
11
12
13
14
7
8
9
8-9) corresponds to an internal interrupt source. When an interrupt is
Description
DMAC Err
GTM1_4
GTM1_2
GTM1_3
GTM1_1
MSIR2
MSIR3
MSIR4
MSIR5
MSIR6
MSIR7
GPIO
Field
DDR
LBC
—
—
—
—
—
—
—
—
Integrated Programmable Interrupt Controller (IPIC)
8-13
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