MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 825

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

14.5.6
This section describes the following registers:
14.5.6.1
PEX_OMBCR, shown in
local host to the PCI Express and indicates that the local host has programmed the data mailbox register,
and it is ready to be read. Setting the ready bit generates an interrupt to the PCI Express host if enabled.
The PCI Express host should clear the ready bit after reading the data mailbox register.
Table 14-106
Freescale Semiconductor
Offset 0xB20
Reset
31–8
Bits
7
6
5
4
3
2
1
0
W
•
•
•
•
R
31
Section 14.5.6.1, “PCI Express Outbound Mailbox Control Register (PEX_OMBCR)”
Section 14.5.6.2, “PCI Express Outbound Mailbox Data Register (PEX_OMBDR)”
Section 14.5.6.3, “PCI Express Inbound Mailbox Control Register (PEX_IMBCR)”
Section 14.5.6.4, “PCI Express Inbound Mailbox Data Register (PEX_IMBDR)”
DSUER Descriptor update error. Hardware sets this bit to indicate an error during descriptor update operation.
CPLER
DAFER
DSFER
DSCPL
CHCPL
Name
BRER
—
—
Mailbox Registers
PCI Express Outbound Mailbox Control Register (PEX_OMBCR)
Figure 14-108. PCI Express Outbound Mailbox Control Register (PEX_OMBCR)
defines the bit fields of PEX_OMBCR.
Reserved
PCI Express completion error. Hardware sets this bit to indicate that DMA operation cannot complete
successfully because of a PCI Express error.
DMA data write error. The hardware sets this bit to indicate an error during data write operation.
Bridge error. Hardware sets this bit to indicate that DMA operation cannot complete successfully because
of a CSB bridge error.
Reserved
Descriptor fetch error. This bit is set by hardware to indicate that a descriptor read from the CSB has
terminated with an error.
Descriptor DMA transfer completed. Hardware sets this bit after completing the transaction for the
descriptor.
DMA chain transfer completed. Hardware sets this bit after completing the transaction in all the descriptors
that are currently programmed. This bit is set when DMA operation is complete and the DMA controller
encounters a NULL descriptor.
Note: When hardware sets this bit it is not guaranteed that the transferred data has fully reached its final
destination. Software should guarantee this another way.
Table 14-105. PEX_RDMA_STAT Register Fields Description
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Figure
14-108, controls the generation of an outbound interrupt from the CSB
—
All zeros
Description
PCI Express Interface Controller
Access: Read/Write
1
READY
0
14-87