MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 194

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

System Configuration
5.5.6.2
The PIT unit can operate in the following modes:
5.5.7
The following initialization sequence of PIT is recommended:
5.6
The following sections describe theory of operation of the general purpose (global) timer module,
including a definition of the external signals and the functionality. Additionally, the configuration, control,
and status registers are described. Note that individual chapters in this book describe additional specific
initialization aspects for each individual block.
There is one global timer (GTM1) with 4 instances as GTM1_1, GTM1_2, GTM1_3, and GTM1_4.
5.6.1
Each global timer module includes four identical 16-bit general-purpose timers, two 32-bit timers or one
64-bit timer. Each GTM timer consists of a timer prescale register (GTPSR), a timer mode register
(GTMDR) a timer capture register (GTCPR), a timer counter register (GTCNR), a timer reference register
5-52
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1. Write to PTPSR to set the PIT prescaler to the desired value
2. Write to PTLDR to initialize the PIT initial value
3. Write to PTCNR to configure and start the PIT operation: PIT input clock source, periodic interrupt
PIT enable/disable mode:
The PTCNR[CLEN] bit enables the PIT timer. It should be set by software after a system reset to
enable the PIT timer.
— PIT disable mode (PTCNR[CLEN] = 0). When the PIT’s clock is disabled, counter maintains
— PIT enable mode (PTCNR[CLEN] = 1). When the counter’s clock is enabled, it continues
PIT periodic interrupt enable/disable mode:
— PIT periodic interrupt enable mode (PTCNR[PIM] = 1). After the PIT’s 32-bit counter reaches
— PIT periodic interrupt disable mode (PTCNR[PIM] = 0). After the PIT’s 32-bit counter reaches
PIT internal/external input clock mode:
The input clock to the PIT may be an internal system clock or the RTC_PIT_CLOCK.
— PIT use the internal input clock mode (PTCNR[CLIN] = 0)
— PIT use the RTC_PIT_CLOCK (PTCNR[CLIN] = 1)
mask, PIT clock enable.
General-Purpose Timers (GTMs)
its old value.
counting using the previous value.
zero, the PIT sets the PTEVR[PIF] flag and generates an interrupt.
zero, the PIT sets the PTEVR[PIF] flag but does not generate an interrupt.
PIT Programming Guidelines
GTM Overview
PIT Operational Modes
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Freescale Semiconductor