MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 124

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Reset, Clocking, and Initialization
4.3.2.2.5
The eTSEC2 mode reset configuration word field, shown in
eTSEC2 controller.
4.3.2.2.6
The true little-endian reset configuration word field, shown in
operates in big-endian mode or true little-endian mode at reset.
4.3.3
The device loads the reset configuration words from a local bus EEPROM, a local bus NAND Flash, or an
I
described in
options.
4.3.3.1
The reset configuration words are assumed to reside in an EEPROM or NOR Flash or NAND Flash device
connected to LCS0 of the device local bus. Because the port size of this EEPROM is unknown, the device
reads all configuration words byte-by-byte only from locations that are independent of port size.
4-16
2
Reset Configuration
Reset Configuration
Word High Register
Word High Register
C serial EEPROM, or uses hard-coded configuration, as selected by the reset configuration inputs
(RCWHR) Bits
(RCWHR) Bit
19–21
28
Loading the Reset Configuration Words
Section 4.3.1, “Reset Configuration Signals.”
Loading from Local Bus
eTSEC2 Mode
e300 Core True Little-Endian
Field Name
Field Name
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
TSEC2M
TLE
Table 4-15. eTSEC2 Mode Configuration
Table 4-16. e300 Core True Little-Endian
(Binary)
(Binary)
Value
Value
000
001
010
011
100
101
110
111
0
1
The eTSEC2 controller operates in the MII protocol, using only four
transmit data signals and four receive data signals.
Reserved
Reserved
The eTSEC2 controller operates in the RGMII protocol, using four
transmit data signals and four receive data signals.
Reserved
Reserved
Reserved
Reserved
Big-endian mode
True little-endian mode
The following sections describe each of these
Table
Table
4-15, selects the protocol used by the
4-16, selects whether the e300 core
Meaning
Meaning
Freescale Semiconductor