MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 34

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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xxxiv
Receive Dropped Packet Counter Register Definition ....................................................... 16-89
Transmit Byte Counter Register Definition ........................................................................ 16-89
Transmit Packet Counter Register Definition ..................................................................... 16-90
Transmit Multicast Packet Counter Register Definition ..................................................... 16-90
Transmit Broadcast Packet Counter Register Definition .................................................... 16-91
Transmit Pause Control Frame Counter Register Definition .............................................. 16-91
Transmit Deferral Packet Counter Register Definition....................................................... 16-92
Transmit Excessive Deferral Packet Counter Register Definition...................................... 16-92
Transmit Single Collision Packet Counter Register Definition .......................................... 16-93
Transmit Multiple Collision Packet Counter Register Definition....................................... 16-93
Transmit Late Collision Packet Counter Register Definition ............................................. 16-94
Transmit Excessive Collision Packet Counter Register Definition .................................... 16-94
Transmit Total Collision Counter Register Definition ........................................................ 16-95
Transmit Drop Frame Counter Register Definition ............................................................ 16-95
Transmit Jabber Frame Counter Register Definition .......................................................... 16-96
Transmit FCS Error Counter Register Definition ............................................................... 16-96
Transmit Control Frame Counter Register Definition ........................................................ 16-97
Transmit Oversized Frame Counter Register Definition .................................................... 16-97
Transmit Undersize Frame Counter Register Definition .................................................... 16-98
Transmit Fragment Counter Register Definition ................................................................ 16-98
Carry Register 1 (CAR1) Register Definition..................................................................... 16-99
Carry Register 2 (CAR2) Register Definition................................................................... 16-100
Carry Mask Register 1 (CAM1) Register Definition........................................................ 16-101
Carry Mask Register 2 (CAM2) Register Definition........................................................ 16-103
Receive Filer Rejected Packet Counter Register Definition ............................................. 16-104
IGADDRn Register Definition ......................................................................................... 16-105
GADDRn Register Definition........................................................................................... 16-105
ATTR Register Definition ................................................................................................. 16-106
ATTRELI Register Definition........................................................................................... 16-107
RQPRM Register Definition............................................................................................. 16-108
RFBPTR0–RFBPTR7 Register Definition........................................................................ 16-108
TMR_CTRL Register Definition ...................................................................................... 16-109
TMR_TEVENT Register Definition................................................................................. 16-112
TMR_PEVENT Register Definition................................................................................. 16-114
TMR_PEMASK Register Definition ................................................................................ 16-114
TMR_CNT_H Register Definition ................................................................................... 16-116
TMR_ADD Register Definition........................................................................................ 16-116
TMR_ACC Register Definition ........................................................................................ 16-117
TMR_PRSC Register Definition ...................................................................................... 16-117
TMROFF_H/L Register Definition .................................................................................. 16-118
TMR_ALARM1-2_H/L Register Definition .................................................................... 16-118
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
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