MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 294

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Integrated Programmable Interrupt Controller (IPIC)
8.5.10
Each bit in the SEPNR, shown in
interrupt is received, the interrupt controller sets the corresponding SEPNR bit.
Table 8-18
8.5.11
The SMPRR_A, shown in
8-20
Offset 0x2C
Reset
Reset
Offset 0x30
Reset 0
0, 1,
4-31
Bits
2, 3
W
W
W
R
R
R
1
2
IRQ0
Name
0
MIXA0P
IRQ n Each bit corresponds to an external interrupt source. When an external interrupt is received, the interrupt
16
This bit is valid only if the IRQ0 signal is configured as an external maskable interrupt (SEMSR[SIRQ0] = 0)
The user should drive all IRQ inputs to an inactive state prior to reset negation
0
—
0
The reset values of implemented bits reflect the values of the external IRQ signals. Reserved bits are zeros.
1
defines the bit fields of SEPNR.
System External Interrupt Pending Register (SEPNR)
System Mixed Interrupt Group A Priority Register (SMPRR_A)
IRQ1 IRQ2 IRQ3
2
0
controller sets the corresponding SEPNR bit.
When a pending interrupt is handled, the user must clear the corresponding SEPNR bit. For level triggered
cases, the software needs to cause the IRQn to negate which automatically clears the bit in SEPNR. For
edge-triggered cases, the software needs to clear the corresponding bit in SEPNR.
SEPNR bits are cleared by writing ones to them. Because the user can only clear bits in this register, writing
zeros to this register has no effect.
Note that the SEPNR bit positions are not changed according to their relative priority.
Write ignored, read = 0
1
Figure 8-14. System Mixed Interrupt Group A Priority Register (SMPRR_A)
0
3
MIXA1P
0
Figure 8-13. System External Interrupt Pending Register (SEPNR)
2
1
5
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
6
0
MIXA2P
Figure
3
1
0
8
4
Figure
Table 8-18. SEPNR Field Descriptions
8-14, defines the priority among the sources listed in
0
9
MIXA3P
1
11 12
8-13, corresponds to an external interrupt source. When an
1
0
0
—
0
All zeros
15 16
0
Description
—
1
MIXA4P
0
18 19
0
1
MIXA5P
—
0
21 22
1
1
MIXA6P
1
24 25
0
Freescale Semiconductor
1
MIXA7P
Table
1
Access: Read/write
Access: Read/write
27 28
1
8-19.
0
0
—
2
0
15
31
31
0