MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 295

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 8-19
8.5.12
SMPRR_B, shown in
Table 8-20
Freescale Semiconductor
Offset 0x34
Reset 0
3–11, 16–27 MIXA1P–MIXA7P Same as MIXA0P, but for MIXA1P–MIXA7P.
0–2, 3–11, 16–27
12–15,
28–31
12–15, 28–31
W
R
Bits
0–2
0
MIXB0P
Bits
0
defines the bit fields of SMPRR_A.
defines the bit fields of SMPRR_B.
System Mixed Interrupt Group B Priority Register (SMPRR_B)
2
0
Figure 8-15. System Mixed Interrupt Group B Priority Register (SMPRR_B)
0
3
MIXB1P
MIXA0P
Name
MIXB n P MIXB n priority order. Defines which interrupt source asserts its request in the MIXB n priority
—
0
Name
—
Figure
1
5
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
6
0
MIXB2P
position. The user must not program the same code to more than one priority position (0–7).
These bits can be changed dynamically. The definition of MIXB n P is as follows:
000 RTC ALR asserts its request to the MIXB n position.
001 Reserved
010 SBA asserts its request to the MIXB n position.
011–111 Reserved
Write ignored, read = 0
1
MIXA0 priority order. Defines which interrupt source asserts its request in the MIXA0 priority
position. The user must not program the same code to more than one priority position (0–7).
These bits can be changed dynamically. The definition of MIXA0P is as follows:
000 RTC SEC asserts its request to the MIXA0 position.
001 PIT asserts its request to the MIXA0 position.
010 Reserved
011 MSIR0 asserts its request to the MIXA0 position.
100 IRQ0 asserts its request to the MIXA0 position. This field for MIXA0 position is valid
101 IRQ1 asserts its request to the MIXA0 position.
110 IRQ2 asserts its request to the MIXA0 position.
111 IRQ3 asserts its request to the MIXA0 position.
Write ignored, read = 0
8-15, defines the priority among the sources listed in
0
8
Table 8-19. SMPRR_A Field Descriptions
Table 8-20. SMPRR_B Field Descriptions
(must not be ignored) if IRQ0 signal configured as an external maskable interrupt
(SEMSR[SIRQ0] = 0).
0
9
MIXB3P
1
11 12
1
0
0
—
0
15 16
0
1
MIXB4P
0
Description
Description
18 19
0
Integrated Programmable Interrupt Controller (IPIC)
1
MIXB5P
0
21 22
1
1
MIXB6P
1
24 25
0
Table
1
MIXB7P
1
Access: Read/write
8-20.
27 28
1
0
0
—
0
8-21
31
0