MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 219

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 6-3
6.2.3
The arbiter uses arbiter event register (AER) to report on erroneous transactions. This register is cleared
by writing ones to the fields to be cleared.
Table 6-4
Freescale Semiconductor
Offset 0x0C
Reset
16–31
0–15
0–25
Bits
Bits
26
27
W
R
0
Name
DTO
ATO
describes ATR fields.
describes AER fields.
Name
ETEA
RES
—
Arbiter Event Register (AER)
Data time out. Specifies the time-out period for the data tenure. The granularity of this field is128 bus clocks.
The maximum value is 8355840 coherent system bus clocks. Data time_out occurs if the data tenure does
not end before the specified time-out period. When DTO = n, the timeout cycle is n × 128.
0000 Reserved
0001 128 clock cycles
0002 256 clock cycles
0003 384 clock cycles
...
FFFF 8355840 clock cycles
Address time out. Specifies the time-out period for the address tenure. The granularity of this field is128 bus
clocks. Maximum value is 8355840 coherent system bus clocks. Address time-out occurs if the address
tenure did not end before the specified time-out period. When ATO = n, the timeout cycle is n × 128.
0000 Reserved
0001 128 clock cycles
0002 256 clock cycles
0003 384 clock cycles
...
FFFF 8355840 clock cycles
Write reserved, read = 0
Transfer error. Reports on detection of transfer error by one of the slaves.
0 No transfer error detected by one of the slaves.
1 Transfer error detected by one of the slaves.
Reserved transfer type. Reports on transaction with reserved transfer type. See
“Reserved Transaction Type,”
0 No transaction with reserved transfer type occurred.
1 Transaction with reserved transfer type occurred.
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Figure 6-3. Arbiter Event Register (AER)
Table 6-4. AER Field Descriptions
Table 6-3. ATR Field Descriptions
—
Figure 6-3
for more information.
All zeros
shows the fields of AER.
Description
Description
25
ETEA RES ECW AO DTO ATO
w1c
26
w1c w1c w1c w1c w1c
27
Section 6.3.2.5,
Arbiter and Bus Monitor
28
Access: User w1c
29
30
31
6-5