MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 849

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Each PCI Express device is divided into two halves, transmit (Tx) and receive (Rx), and each of these
halves is further divided into three layers—transaction, data link, and physical—as shown in
Figure
Packets are formed in the transaction layer (TL) and data link layer (DLL), and each subsequent layer adds
the necessary encoding and framing. As packets are received, they are decoded and processed by the same
layers but in reverse order, so they may be processed by the layer or by the device application software.
14.6.1
This section contains the following:
Freescale Semiconductor
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14-138.
Section 14.6.1.1, “Address Translation Windows (ATMUs)”
Section 14.6.1.2, “PCI Express Transactions”
Section 14.6.1.3, “Byte Swapping”
Section 14.6.1.4, “Outbound Byte Swapping”
Section 14.6.1.5, “Inbound Byte Swapping”
Section 14.6.1.6, “Transaction Ordering Rule”
Section 14.6.1.7, “Memory Space Addressing”
Architecture
Framing
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Sequence
Number
Figure 14-138. PCI Express High-Level Layering
Electrical Sub-Block
Logical Sub-Block
RX
Figure 14-139. PCI Express Packet Flow
Transaction
Data Link
Physical
Header
TX
Transaction Layer
Data Link Layer
Physical Layer
Data
Electrical Sub-Block
Logical Sub-Block
RX
Transaction
Data Link
Physical
ECRC
TX
LCRC
PCI Express Interface Controller
Framing
14-111