MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 1021

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The transmit timer threshold counter is reset to the value in TXIC[ICTT] and begins counting down on
transmission of the frame following an interrupt.
The receive timer threshold counter is reset to the value in RXIC[ICTT] and begins counting down on
receiving the frame following an interrupt.
16.6.2.10 Inter-Frame Gap Time
If a station must transmit, it waits until the LAN becomes silent for a specified period (inter-frame gap, or
IFG). The minimum inter-packet gap (IPG) time for back-to-back transmission is set by
IPGIFG[Back-to-Back Inter-Packet-Gap]. The receiver receives back-to-back frames with the minimum
interframe gap (IFG) as set in IPGIFG[Minimum IFG Enforcement]. If multiple frames are ready to
transmit, the Ethernet controller follows the minimum IPG as long as the following restrictions are met:
If the first TxBD alignment restriction is not met, the back-to-back IPG may be as many as 32 cycles. If
the TxBD size restriction is not met, the back-to-back IPG may be significantly longer.
In half-duplex mode, after a station begins sending, it continually checks for collisions on the LAN. If a
collision is detected, the station forces a jam signal (all ones) on its frame and stops transmitting. Collisions
usually occur close to the beginning of a packet. The station then waits a random time period (back-off)
before attempting to send again. After the back-off completes, the station waits for silence on the LAN
(carrier sense negated) and then begins retransmission (retry) on the LAN. Retransmission begins 36 bit
times after carrier sense is negated for at least 60 bit times. If the frame is not successfully sent within a
specified number of retries, an error is indicated (collision retry limit exceeded).
16.6.2.11 Internal and External Loop Back
Setting MACCFG1[Loop Back] causes the MAC transmit outputs to be looped back to the MAC receive
inputs. Clearing this bit results in normal operation. This bit is cleared by default. Clearing this bit results
in normal operation.
For loopback, TX_CLK is required (from the Ethernet PHY) and RX_CLK is not required. The output data
appears on the TX pin.
Freescale Semiconductor
(Clock Source)
1 (sys. clock)
0 (I/F clock)
0 (I/F clock)
0 (I/F clock)
•
•
ICCS
The first TxBD pointer, TBPTRn, of any given frame is located at a 16-byte aligned address.
Each TxBD[Data Length] is greater-than or equal to 64 bytes.
10Base-T at 2.5 MHz
100Base-T at 25 MHz
1000Base-T at 125 MHz
eTSEC operating at 125 MHz
eTSEC Interface Format and
eTSEC System Frequency
Table 16-133. Interrupt Coalescing Timing Threshold Ranges
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Frequency or
Minimum (ICTT = 0x0001)
0.512 μs
25.6 μs
2.56 μs
0.51 μs
Interrupt Coalescing Threshold Time
Enhanced Three-Speed Ethernet Controllers
Maximum (ICTT = 0xFFFF)
33.6 ms
33.5 ms
168 ms
1.68 s
16-137