MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 943

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16.5.3.3.9
The MRBLR register is written by the user. It informs the eTSEC how much space is in the receive buffer
pointed to by the RxBD.
Freescale Semiconductor
1
1011 0–23
1100 0–31
1101 0–31
1110 0–15
1111 0–15
PID
16–25
26–31
0–15
\\
Bits
PID is the property identifier field of the filer table control entry (see RQFCR[PID]) at the same index.
Offset eTSEC1:0x2_4340; eTSEC2:0x2_5340
Reset
1
24–31
16–31
16–31
W
R
Bit
MRBL Maximum receive buffer length. MRBL is the number of bytes that the eTSEC receiver writes to the receive
Name
0
—
—
Name
DPT
SPT
L4P
DIA
SIA
—
—
—
Maximum Receive Buffer Length Register (MRBLR)
Reserved
buffer. The MRBL register is written by the user with a multiple of 64 for all modes. The eTSEC can write fewer
bytes to the buffer than the value set in MRBL if a condition such as an error or end-of-frame occurs, but it
never exceeds the MRBL value; therefore, user-supplied buffers must be at least as large as the MRBL. MRBL
must be set, together with the number of buffer descriptors, to ensure adequate space for received frames.
See
To ensure that MRBL is a multiple of 64, these bits are reserved and should be cleared.
Section 16.5.3.5.5, “Maximum Frame Length Register
Reserved, should be written with zero.
Layer 4 protocol identifier as per published IANA specification. This is the last recognized protocol type
recognized in the case of IPv6 extension headers. This value defaults to 0xFF to indicate that no layer
4 header was recognized (possibly due to absence of an IP header).
Destination IP address. If an IPv4 header was found, this is the entire destination address. If an IPv6
header was found, this is the 32 most significant bits of the 128-bit destination address. This value
defaults to 0x0000_0000 if no IP header appeared.
Source IP address. If an IPv4 header was found, this is the entire source address. If an IPv6 header was
found, this is the 32 most significant bits of the 128-bit source address. This value defaults to
0x0000_0000 if no IP header appeared.
Reserved, should be written with zero.
Destination port number for TCP or UDP headers. This value defaults to 0x0000 if no TCP or UDP
headers were recognized.
Reserved, should be written with zero.
Source port number for TCP or UDP headers. This value defaults to 0x0000 if no TCP or UDP headers
were recognized.
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Figure 16-31
Table 16-34. RQFPR Field Descriptions (continued)
—
Figure 16-31. MRBLR Register Definition
Table 16-35. MRBLR Field Descriptions
describes the definition for the MRBLR.
All zeros
15 16
Description
Description
(MAXFRM),” for further discussion.
MRBL
Enhanced Three-Speed Ethernet Controllers
25 26
Access: Read/Write
—
16-59
31