MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 81

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The eSDHC acts as a bridge, passing host bus transactions to SD/SDIO/MMC cards by sending commands
and performing data accesses to or from the cards. It handles the SD/SDIO/MMC protocol at the
transmission level.
The eSDHC can select the following modes for data transfer:
1.2.13
The system includes the following timers:
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audio and video consumer electronic devices. The physical form factor, pin assignments, and data
transfer protocol are forward-compatible with the old MMC.
SDIO
Under the SD protocol, the SD cards can be categorized as a memory card, I/O card, or combo card.
The memory card invokes a copyright protection mechanism that complies with the security of the
SDMI standard. The I/O card provides high-speed data I/O with low power consumption for
mobile electronic devices. The combo card has both memory and I/O functions.
SD 1-bit
SD 4-bit
MMC 1-bit
MMC 4-bit
Identification mode (up to 400 KHz)
Full-speed mode (up to 25 MHz) or high-speed mode (up to 50 MHz)
Periodic interrupt timer
Real time clock
Software watchdog timer
One general-purpose timer block, supporting four 16-bit programmable timers or two cascaded
32-bit timers, or one cascaded 64-bit counter
System Timers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Overview
1-17