MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 400

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Enhanced Local Bus Controller
10-20
10–12
14–17
18–21
Bits
8–9
13
Name
G0CL General line 0 control. Determines which logical address line can be output to the LGPL0 pin when the UPM n
GPL4
WLF
RLF
DS
Disable timer period. Guarantees a minimum time between accesses to the same memory bank controlled
by UPM n . The disable timer is turned on by the TODT bit in the RAM array word, and when expired, the UPM n
allows the machine access to handle a memory pattern to the same bank. Accesses to a different bank by
the same UPM n is also allowed. To avoid conflicts between successive accesses to different banks, the
minimum pattern in the RAM array for a request serviced, should not be shorter than the period established
by DS.
00 1-bus clock cycle disable period
01 2-bus clock cycle disable period
10 3-bus clock cycle disable period
11 4-bus clock cycle disable period
is selected to control the memory access.
000 A12
001 A11
010 A10
011 A9
100 A8
101 A7
110 A6
111 A5
LGPL4 output line disable. Determines how the LGPL4/LUPWAIT pin is controlled by the corresponding bits
in the UPM n array. See
Read loop field. Determines the number of times a loop defined in the UPM n will be executed for a burst- or
single-beat read pattern or when M x MR[OP] = 11 (
0000 16
0001 1
0010 2
0011 3
...
1110 14
1111 15
Write loop field. Determines the number of times a loop defined in the UPM n will be executed for a burst- or
single-beat write pattern.
0000 16
0001 1
0010 2
0011 3
...
1110 14
1111 15
Value
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
0
1
Table 10-11. M x MR Field Descriptions (continued)
LGPL4/LUPWAIT
LUPWAIT (input)
LGPL4 (output)
Pin Function
Table 10-40 on page
Interpretation of UPM Word Bits
G4T1/DLT3
10-75.
Description
G4T1
DLT3
RUN
command)
G4T3/WAEN
WAEN
G4T3
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