MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 936

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
16.5.3.3.5
The RBIFX register provides a set of four 6-bit offsets for locating up to four octets in a received frame
and passing them to the receive queue filer as the user-defined ARB property. Through RBIFX a custom
ARB filer property can be constructed from arbitrary bytes, which allows frame filing on the basis of bit
fields not ordinarily provided to the filer, such as bits from the Ethernet preamble or TCP flags. The value
of property ARB is the concatenation of {B0, B1, B2, B3} to 32-bits, where B0–B3 are the bytes as defined
by RBIFX.
Figure 16-26
Table 16-31
16-52
Offset eTSEC1:0x2_4330; eTSEC2:0x2_5330
Reset
16–23
24–31
Bits
Bits
0–1
2–7
W
R
B0CTL
0
Name
B0OFFSET Offset relative to the header defined by B0CTL that locates byte 0 of property ARB. An effective offset
EN n
—
1
B0CTL
Name
describes the RBIFX register.
describes the definition for the RBIFX register.
2
Receive Bit Field Extract Control Register (RBIFX)
Reserved
Receive queue n enable.
0 RxBD ring is not queried for reception. In effect the receive queue is disabled.
1 RxBD ring is queried for reception.
B0OFFSET
00 Byte 0 is not extracted, and appears as zero in property ARB.
01 Byte 0 is located in the received frame at offset (B0OFFSET – 8) bytes from the first byte of the
10 Byte 0 is located in the received frame at offset B0OFFSET bytes from the byte after the last byte of
11 Byte 0 is located in the received frame at offset B0OFFSET bytes from the byte after the last byte of
of zero points to the first byte of the specified header.
Location of byte 0 of property ARB.
Ethernet DA. In non-FIFO modes, a negative effective offset points to bytes of the standard Ethernet
preamble. Values of B0OFFSET less than 8 are reserved in FIFO modes.
the layer 2 header.
the layer 3 header.
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Table 16-30. RQUEUE Field Descriptions (continued)
7
B1CTL
8
Figure 16-26. RBIFX Register Definition
Table 16-31. RBIFX Field Descriptions
9
10
B1OFFSET
All zeros
15 16
Description
B2CTL
Description
17 18
B2OFFSET
23 24
B3CTL
Freescale Semiconductor
25 26
Access: Read/Write
B3OFFSET
31