MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 562

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DMA Controller (DMAC)
Figure 12-16
Table 12-17
When minor loop mapping (DMACR[EMLM] = 1) is enabled, TCD word2, shown in
redefined as four fields: a source minor loop offset enable, a destination minor loop offset enable, a minor
loop offset field, and a nbytes field.
12-18
Offset DMA_Offset = 0x1000 + (32 × n ) + 0x04
Reset
Reset
31–27
26–24
23–19
18–16
15–0
Bits
W
W
R
R
31
15
Name
smod
dmod
dsize
ssize
soff
Table 12-17. TCD Word 1 (TCD.{smod, ssize, dmod, dsize, soff}) Field Descriptions
describes the TCD word 1 fields.
shows the TCD word 1 field.
Source address modulo.
0
Other The value defines a specific address bit which is selected to be either the value after saddr + soff
Source data transfer size.
000 8-bit
001 16-bit
010 32-bit
011 64-bit
100 16-byte
100 Reserved
101 32-byte
110 Reserved
111 Reserved
Destination address modulo. See the smod definition.
Destination data transfer size. See the ssize definition.
Source address signed offset. Sign-extended offset applied to the current source address to form the
next-state value as each source read is completed.
Figure 12-16. TCD Word 1 (TCDn.{soff, smod, ssize, dmod, dsize}) Fields
smod[4–0]
Source address modulo feature is disabled.
calculation is performed or the original register value. This feature provides the ability to easily
implement a circular data queue. For data queues requiring power-of-2 ‘size’ bytes, the queue should
be based at a 0-modulo-size address and the smod field set to the appropriate value to freeze the
upper address bits. The bit select is defined as ((1 << smod[4:0]) – 1) where a resulting 1 in a bit
location selects the next state address for the corresponding address bit location and a 0 selects the
original register value for the corresponding address bit location. For this application, the soff is
typically set to the transfer size to implement post-increment addressing with the smod function
constraining the addresses to a 0-modulo-size range.
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
27
26
ssize[2–0]
24
soff[15–0]
All zeros
All zeros
Description
23
dmod[4–0]
19
Freescale Semiconductor
Figure
Access: Read/Write
18
dsize[2–0]
12-17, is
16
0