MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 428

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Enhanced Local Bus Controller
example, when ACS = 00 and CSNT = 1, LWEn is negated one quarter of a clock earlier, as shown in
Figure
If LCRR[CLKDIV] = 2, LCSn and LWEn are negated one cycle earlier if TRLX = 1.
For example, when ACS = 00, CSNT = 1 and TRLX = 0, LWEn is negated one quarter of a clock earlier
and LCSn is negated normally as shown in
10.4.2.3.3
ORx[TRLX] is provided for memory systems that require more relaxed timing between signals. Setting
TRLX = 1 has the following effect on timing:
Figure 10-37
LCRR[CLKDIV] = 2 for these examples is only to delay the assertion of LCSn in the ACS = 10 case to
the ACS = 11 case. The example in
pair of writes issued consecutively.
10-48
1. LCSn is affected by CSNT and TRLX only if ACS[0] is non zero. However, LWEn is affected
2. When CSNT attribute is asserted, the strobe is negated one quarter of a clock before the normal
3. TRLX = 1 in conjunction with CSNT = 1, negates the LWEn 1+1/4 cycle earlier if
•
•
•
•
•
10-36. If LCRR[CLDIV] = 2, LWEn is negated coincident with LCSn.
independent of ACS.
case provided that LCRR[CLDIV] = 4 or 8.
LCRR[CLKDIV] = 4 or 8.
An additional bus cycle is added between the address and control signals (but only if ACS is not
equal to 00).
The number of wait states specified by SCY is doubled, providing up to 30 wait states.
The extended hold time on read accesses (EHTR) is extended further.
LCSn signals are negated one cycle earlier during writes (but only if ACS is not equal to 00).
LWE[0:1] signals are negated one cycle earlier during writes.
and
Relaxed Timing
Figure 10-38
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
show relaxed timing read and write transactions. The effect of
Figure 10-38
Figure
also shows address and data multiplexing on LD for a
10-36.
Freescale Semiconductor