MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 179

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Although most software disciplines permit or even encourage the watchdog concept, some systems require
a selection of time-out periods. For this reason, the software watchdog timer must provide a selectable
range for the time-out period.
Figure 5-26
into a 16-bit decrementer clocked by the system clock. An additional divide-by-65,536 prescaler value is
used when needed.
The decrementer begins counting when loaded with a value from SWTC. After the timer reaches 0x0, a
software watchdog expiration request is issued to the reset or mcp (machine check) control logic. Upon
reset, SWTC is set to the maximum value and is again loaded into the system watchdog service register
(SWSRR), starting the process over. When a new value is loaded into SWTC, the software watchdog timer
is not updated until the servicing sequence is written to the SWSRR. If SWCRR[SWEN] is loaded with 0,
the modulus counter does not count.
5.3.5.2
The WDT unit can operate in the following modes:
Freescale Semiconductor
•
•
Clocking
System
WDT enable/disable mode:
If the software watchdog timer is not needed, the user can disable it. The SWCRR[SWEN] bit
enables the watchdog timer. It should be cleared by software after a system reset to disable the
software watchdog timer. When the watchdog timer is disabled, the watchdog counter and
prescaler counter are held in a stopped state.
— WDT enable mode (SWCRR[SWEN] = 1)
— WDT disable mode (SWCRR[SWEN] = 0)
WDT reset/interrupt output mode
Without software periodic servicing, the software watchdog timer times out and issues a reset or a
nonmaskable interrupt (mcp), programmed in SWCRR[SWRI].
– Default value after hard reset
– Selectable by RCWHR[8].
shows that the range is determined by SWCRR[SWTC]. The value in SWTC is then loaded
Modes of Operation
SWCRR[SWEN]
Disable
Clock
Figure 5-26. Software Watchdog Timer Functional Block Diagram
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Figure 5-26
65,536
Divider
shows how to handle this need.
SWCRR[SWPR]
16-Bit Decrementer
SWCRR[SWTC]
SWSRR[WS]
SWCNR
Service
Reload
Time-out
SWCRR[SWRI]
System Configuration
or mcp
Reset
Event
Logic
5-37