MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 676

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface
13.6.12.2.4 Tracking Split Transaction Progress for Interrupt Transfers
To correctly maintain the data stream, the host controller must be able to detect and report errors where
data is lost. For interrupt-IN transfers, data is lost when it makes it into the USB 2.0 hub, but the USB 2.0
host system is unable to get it from the USB 2.0 hub and into the system before it expires from the
transaction translator pipeline. When a lost data condition is detected, the queue is halted, thus signaling
system software to recover from the error. A data-loss condition exists whenever a start-split is issued,
accepted and successfully executed by the USB 2.0 hub, but the complete-splits get unrecoverable errors
on the high-speed link, or the complete-splits do not occur at the correct times. One reason complete-splits
might not occur at the right time would be due to host-induced system hold-offs that cause the host
controller to miss bus transactions because it cannot get timely access to the schedule in system memory.
The same condition can occur for an interrupt-OUT, but the result is not an endpoint halt condition, but
rather effects only the progress of the transfer. The queue head has the following fields to track the progress
of each split transaction. These fields are used to keep incremental state about which (and when) portions
have been executed.
13.6.12.2.5 Split Transaction Execution State Machine for Interrupt
In the following section, all references to microframe are in the context of a microframe within an
H-Frame.
As with asynchronous Full- and Low-speed endpoints, a split-transaction state machine is used to manage
the split transaction sequence. Aside from the fields defined in the queue head for scheduling and tracking
the split transaction, the host controller calculates one internal mechanism that is also used to manage the
split transaction. The internal calculated mechanism is:
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C-prog-mask. This is an eight-bit bit-vector where the host controller keeps track of which
complete-splits have been executed. Due to the nature of the transaction translator periodic
pipeline, the complete-splits need to be executed in-order. The host controller needs to detect when
the complete-splits have not been executed in order. This can only occur due to system hold-offs
where the host controller cannot get to the memory-based schedule. C-prog-mask is a simple
bit-vector that the host controller sets one of the C-prog-mask bits for each complete-split
executed. The bit position is determined by the microframe number in which the complete-split
was executed. The host controller always checks C-prog-mask before executing a complete-split
transaction. If the previous complete-splits have not been executed then it means one (or more)
have been skipped and data has potentially been lost.
FrameTag. This field is used by the host controller during the complete-split portion of the split
transaction to tag the queue head with the frame number (H-Frame number) when the next
complete split must be executed.
S-bytes. This field can be used to store the number of data payload bytes sent during the start-split
(if the transaction was an OUT). The S-bytes field must be used to accumulate the data payload
bytes received during the complete-splits (for an IN).
cMicroFrameBit. This is a single-bit encoding of the current microframe number. It is an eight-bit
value calculated by the host controller at the beginning of every microframe. It is calculated from
the three least significant bits of the FRINDEX register (that is, cMicroFrameBit = (1
shifted-left(FRINDEX[2–0]))). The cMicroFrameBit has at most one bit asserted, which always
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Freescale Semiconductor