MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 594

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface
13.3.2.4
In host mode, the frame index register is used by the controller to index the periodic frame list. The register
updates every 125 microseconds (once each microframe). Bits N–3 are used to select a particular entry in
the periodic frame list during periodic schedule execution. The number of bits used for the index depends
on the size of the frame list as set by system software in USBCMD[FS].
13-16
Bits
8
7
6
5
4
3
2
1
0
Name
SRE
URE
PCE
UEE
AAE
SEE
FRE
SLE
UE
Frame Index Register (FRINDEX)
Sleep enable. This is a non-EHCI bit. When this bit is a one, and USBSTS[SLI] transitions, the USB DR
controller issues an interrupt. The interrupt is acknowledged by software writing a one to USBSTS[SLI].
Only used in device mode.
0 Disable
1 Enable
SOF received enable. This is a non-EHCI bit. When this bit is a one, and USBSTS[SRI] is a one, the
controller issues an interrupt. The interrupt is acknowledged by software clearing USBSTS[SRI].
0 Disable
1 Enable
USB reset enable. This is a non-EHCI bit. When this bit is a one, USBSTS[URI] is a one, the device
controller issues an interrupt. The interrupt is acknowledged by software clearing USBSTS[URI] bit. Only
used in device mode.
0 Disable
1 Enable
Interrupt on async advance enable. When this bit is a one, and USBSTS[AAI] is a one, the controller issues
an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing
USBSTS[AAI]. Only used in host mode.
0 Disable
1 Enable
System error enable. When this bit is a one, and USBSTS[SEI] is a one, the controller issues an interrupt.
The interrupt is acknowledged by software clearing USBSTS[SEI].
0 Disable
1 Enable
Frame list rollover enable. When this bit is a one, and USBSTS[FRI] is a one, the controller issues an
interrupt. The interrupt is acknowledged by software clearing USBSTS[FRI]. Only used by the host mode.
0 Disable
1 Enable
Port change detect enable. When this bit is a one, and USBSTS[PCI] is a one, the controller issues an
interrupt. The interrupt is acknowledged by software clearing USBSTS[PCI].
0 Disable
1 Enable
USB error interrupt enable. When this bit is a one, and USBSTS[UEI] is a one, the controller issues an
interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing USBSTS[UEI].
0 Disable
1 Enable
USB interrupt enable. When this bit is a one, and USBSTS[UI] is a one, the DR controller issues an interrupt
at the next interrupt threshold. The interrupt is acknowledged by software clearing USBSTS[UI].
0 Disable
1 Enable
Table 13-12. USBINTR Register Field Descriptions (continued)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Description
Freescale Semiconductor