MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 500

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Enhanced Secure Digital Host Controller
There are three ways to restart the transfer after a stop at the block gap. The appropriate method depends
on whether the eSDHC issues a suspend command or the SD card accepts the suspend command:
Any time PROCTL[SABGREQ] stops the data transfer, the host driver should wait for IRQSTAT[TC]
before attempting to restart the transfer. When restarting the data transfer by continue request, the host
driver should clear PROCTL[SABGREQ] before or simultaneously.
11.4.9
The system control register is shown in
Table 11-13
11-20
Offset: 0x02C (SYSCTL)
Reset
Reset
•
•
•
0–3
Bit
W
W
4
R
R
If the host driver does not issue a suspend command, the continue request should be used to restart
the transfer.
If the host driver issues a suspend command and the SD card accepts it, a resume command should
be used to restart the transfer.
If the host driver issues a suspend command and the SD card does not accept it, PROCTL[CREQ]
should be used to restart the transfer.
16
0
1
0
System Control Register (SYSCTL)
describes the SYSCTL fields.
Name
INITA
0
0
—
—
0
0
Reserved
Initialization active. When this bit is written ‘1’, 80 SD clocks are sent to the card. After the 80 clocks
are sent, this bit is self-cleared. This bit is very useful during the card power-up period when 74 SD
clocks are needed and clock auto-gating feature is enabled.
Writing one to this bit when it is already set has no effect. Clearing this bit at any time does not affect
it. When PRSSTAT[CIHB] or PRSSTAT[CDIHB] is set, writing a one to this bit is ignored. That is,
when the command line or data line is active, writing to this bit is not allowed.
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
SDCLKFS
0
0
3
Figure 11-11. System Control Register (SYSCTL)
INITA
0
0
4
Table 11-13. SYSCTL Field Descriptions
RSTD RSTC RSTA
0
0
5
Figure
0
0
6
11-11.
23
0
0
7
24
0
0
8
Description
0
0
DVS
—
0
0
11
27
0
0
CLKE
12
28
N
0
1
PEREN HCKEN IPGEN
Freescale Semiconductor
29
0
0
DTOCV
Access: Mixed
30
0
0
15
31
0
0