MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 497

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

11.4.8
The protocol control register is shown in
Freescale Semiconductor
Offset: 0x028 (PROCTL)
Reset
Reset
Bit
30
31
W
W
R
R
16
0
0
0
Protocol Control Register (PROCTL)
CDIHB
Name
CIHB
The host driver can issue CMD0, CMD12, CMD13 (for memory) and
CMD52 (for SDIO) when the SD_DAT lines are busy during a data transfer.
These commands can be issued when PRSSTAT[CIHB] is cleared. Other
commands should be issued when PRSSTAT[CDIHB] is cleared. Possible
changes to the SD Physical Specification may add other commands to this
list in the future.
0
0
Command inhibit (SD_DAT). This bit is set if the SD_DAT line is active, the read transfer active is
set, or read wait is asserted. If this bit is cleared, it indicates the eSDHC can issue the next
SD/MMC command. Commands with busy signal belong to command inhibit (SD_DAT) (e.g. R1b
and R5b type). Clearing from 1 to 0 generates a transfer complete interrupt.
Note: The SD host driver can save registers for a suspend transaction after this bit has cleared
0 Can issue command which uses the SD_DAT line
1 Cannot issue command which uses the SD_DAT line
Command inhibit (SD_CMD). This bit is cleared, if the SD_CMD line is not in use and the eSDHC
can issue a SD/MMC command using the SD_CMD line.
This bit is set immediately after the XFERTYP register is written. This bit is cleared when the
command response is received. Even if the CDIHB bit is set, commands using only the SD_CMD
line can be issued if this bit is cleared. Clearing from 1 to 0 generates a command complete
interrupt.
If the eSDHC cannot issue the command because of a command conflict error (refer to command
CRC error) or because of command not issued by Auto CMD12 error, this bit remains set and
IRQSTAT[CC] is not set. Status issuing Auto CMD12 is not read from this bit.
0 Can issue command using only SD_CMD line
1 Cannot issue command
—
0
0
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Table 11-11. PRSSTAT Field Descriptions (continued)
from 1 to 0.
Figure 11-10. Protocol Control Register (PROCTL)
0
0
—
0
0
4
CRM
WE
0
0
5
Figure
CINS
WE
6
0
0
11-10.
NOTE
CINT
WE
23
0
0
7
Description
CDSS CDTL
24
0
0
8
25
0
0
—
26
0
1
EMODE
Enhanced Secure Digital Host Controller
11
27
0
0
D3CD
IABG
12
28
0
0
CTL
Access: Read/Write
RW
13
29
0
0
DTW
CREQ
14
30
0
0
SABG
11-17
REQ
—
15
31
0
0