MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 915

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 16-12
16.5.3.1.7
PTV is a 32-bit register written by the user to store the pause duration used when the eTSEC initiates an
IEEE 802.3 PAUSE control frame through TCTRL[TFC_PAUSE]. The low-order 16 bits (PT) represent
the pause time and the high-order 16 bits (PTE) represent the extended pause control parameter. The pause
time is measured in units of pause_quanta, equal to 512 bit times. The pause time can range from 0 to
65,535 pause_quanta, or 0 to 33,553,920 bit times. See
details.
Freescale Semiconductor
20–24
29–31
Bits
19
25
26
27
28
Figure 16-8
R100M
GMIIM
Name
STEN
RPM
lists the different interface configurations indicated by registers, ECNTRL and MACCFG2.
—
—
—
Pause Time Value Register (PTV)
RGMII 1 Gbps
RGMII 100 Mbps
RGMII 10 Mbps
MII 10/100 Mbps
MIB counter statistics enabled.
0 Statistics not enabled
1 Enables internal counters to update
This is a steady state signal and must be set prior to enabling the Ethernet controller and must not be
changed without proper care.
Reserved
GMII interface mode. If this bit is set, a PHY with a RGMII interface is expected to be connected. If
cleared, a PHY with an MII interface is expected. The user should then set MACCFG2[I/F Mode]
accordingly. The state of this status bit is defined during power-on reset. See
Configuration Words.”
0 MII mode interface expected
1 RGMII mode interface expected
Reserved
Reduced-pin mode for Gigabit interfaces. If this bit is set, a reduced-pin interface is expected on
Ethernet interfaces. This register can be pin-configured at reset to 0 or 1.
0 MII in non-reduced-pin mode configuration
1 RGMII reduced-pin mode
RGMII 100 mode. This bit is ignored unless RPM are set and MACCFG2[I/F Mode] is assigned to
10/100 (01).
0
1
Reserved
describes the definition for the PTV register.
Interface Mode
RGMII is in 10 Mbps mode
RGMII is in 100 Mbps mode
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Table 16-11. ECNTRL Field Descriptions (continued)
Table 16-12. eTSEC Interface Configurations
GMIIM
1
1
1
0
ECNTRL Field
RPM
1
1
1
0
Section 16.6.2.8, “Flow Control,”
Description
R100M
0
1
0
0
Enhanced Three-Speed Ethernet Controllers
MACCFG2 Field
I/F Mode
10
01
01
01
Section 4.3.2, “Reset
for additional
16-31