MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 996

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
Table 16-110
16-112
Offset eTSEC1:0x2_4E04
Reset
Reset
16–23
27–31
8–13
Bits
0–5
14
15
24
25
26
W
W
6
7
R
R
16
0
Name
ALM2
ALM1
ETS2
ETS1
PP1
PP2
PP3
describes the fields of the TMR_TEVENT register fields for the timer.
—
—
—
—
Reserved
External trigger 2 timestamp sampled
0 external trigger timestamp not sampled
1 external trigger timestamp sampled
External trigger 1 timestamp sampled
0 external trigger timestamp not sampled
1 external trigger timestamp sampled
Reserved
Current time equaled alarm time register 2
0 alarm time has not be reached yet
1 alarm time has been reached
Current time equaled alarm time register 1
0 alarm time has not be reached yet
1 alarm time has been reached
Reserved
Indicates that a periodic pulse has been generated based on FIPER1 register.
0 periodic pulse not generated
1 periodic pulse generated
Indicates that a periodic pulse has been generated based on FIPER2 register.
0 periodic pulse not generated
1 periodic pulse generated
Indicates that a periodic pulse has been generated based on FIPER3 register.
0 periodic pulse not generated
1 periodic pulse generated
Reserved
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Table 16-110. TMR_TEVENT Register Field Descriptions
—
Figure 16-106. TMR_TEVENT Register Definition
—
5
ETS2
w1c
6
All zeros
All zeros
ETS1
w1c
23
7
Description
PP1
w1c
24
8
PP2
w1c
25
PP3
w1c
26
—
27
Freescale Semiconductor
13
—
ALM2 ALM1
w1c
Access: w1c
14
w1c
15
31