MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 769

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 14-28
14.4.3.9
The memory limit register is shown in
Table 14-29
14.4.3.10 PCI Express Prefetchable Memory Base Register (RC Mode Only)
The prefetchable memory base register is shown in
Freescale Semiconductor
Offset 0x024
Offset 0x022
Reset
Reset
15–4
15–4
Bits
Bits
3–0
3–0
W
W
R
R
Memory
Memory
15
15
Name
Name
Base
Limit
—
—
describes the memory base register fields.
describes the memory base register fields.
PCI Express Memory Limit Register (RC Mode Only)
Specifies bits 31–20 of the non-prefetchable memory space start address. Typically used for specifying
memory-mapped I/O space.
Note: Inbound posted transactions hitting into the mem base/limit range are ignored; inbound non-posted
Reserved
Specifies bits 31–20 of the non-prefetchable memory space ending address. Typically used for specifying
memory-mapped I/O space.
Note: Inbound posted transactions hitting into the mem base/limit range are ignored; inbound non-posted
Reserved
Table 14-28. PCI Express Memory Base Register Fields Description
Table 14-29. PCI Express Memory Limit Register Fields Description
Figure 14-31. PCI Express Prefetchable Memory Base Register
transactions hitting into the mem base/limit range results in an unsupported request response.
transactions hitting into the mem base/limit range result in an unsupported request response.
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Figure 14-30. PCI Express Memory Limit Register
PF Memory Base
Memory Limit
Figure
14-30.
Figure
All zeros
All zeros
Description
Description
14-31.
4
4
PCI Express Interface Controller
3
3
Address Decode Type
Access: Read/Write
Access: Read/Write
—
14-31
0
0