MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 684

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface
The B-Frame boundaries are marked with a large, bold, dashed line. The bottom of
the relationship of an siTD to the H-Frame.
When the endpoint is an isochronous OUT, there are only start-splits, and no complete-splits. When the
endpoint is an isochronous IN, there is at most one start-split and one to N complete-splits. The scheduling
boundary cases are:
13-106
•
•
Periodic Schedule
Start & Complete
End of H-Frame
Frame Wrap at
Micro-Frame 0
HS/FS/LS Bus
Case 1: The entire split transaction is completely bounded by an H-Frame. For example, the
start-splits and complete-splits are all scheduled to occur in the same H-Frame.
Case 2a: This boundary case is where one or more (at most two) complete-splits of a split
transaction IN are scheduled across an H-Frame boundary. This can only occur when the split
transaction has the possibility of moving data in B-Frame, microframes 6 or 7 (H-Frame
microframe 7 or 0). When an H-Frame boundary wrap condition occurs, the scheduling of the split
Normal Case
Micro-Frame
Micro-Frame
in H-Frame,
Case 2b:
Case 2a:
Case 1:
Figure 13-57. Split Transaction, Isochronous Scheduling Boundary Conditions
B-Frame N–1
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MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
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H-Frame N
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siTD
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B-Frame N
x
OUT
IN
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OUT
Figure 13-57
S
IN
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2
6
H-Frame N+1
Freescale Semiconductor
siTD
1
0
C
3
B-Frame N+1
x+1
illustrates