MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 266

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

e300 Processor Core Overview
7-34
External interrupt
Alignment
Program
Floating-point
unavailable
Decrementer
Critical interrupt
Reserved
System call
Trace
Reserved
Performance
monitor
Instruction
translation miss
Data load
translation miss
Interrupt Type
00500
00600
00700
00800
00900
00A00
00B00–00BFF
00C00
00D00
00E00
00F00
01000
01100
Vector Offset
(hex)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Table 7-8. Exceptions and Interrupts (continued)
Caused when MSR[EE] = 1 and the int signal is asserted.
Caused when the core cannot perform a memory access for any of the reasons described
below:
Caused by one of the following exception conditions, which correspond to bit settings in
SRR1 and arise during execution of an instruction.
Floating-point enabled exception—A floating-point enabled exception condition is
generated when the following condition is met:
Caused by an attempt to execute a floating-point instruction (including floating-point load,
store, and move instructions) when the floating-point available bit (MSR[FP]) is cleared.
Occurs when DEC[0] changes from 0 to 1. This interrupt is enabled with MSR[EE].
Taken when cint is asserted and MSR[CE] = 1.
Occurs when a System Call (sc) instruction is executed.
Taken when MSR[SE] =1 or when the currently completing instruction is a branch and
MSR[BE] =1.
vector for floating-point assist interrupts.
Caused when a configured PM counter using the pm_event_in to transition overflows.
Caused when the effective address for an instruction fetch cannot be translated by the
ITLB.
Caused when the effective address for a data load operation cannot be translated by the
DTLB.
The e300 core does not generate an interrupt to this vector. Other devices may use this
• The operand of a floating-point load or store instruction is not word-aligned.
• The operands of lmw, stmw, lwarx, and stwcx. instructions are not aligned.
• The instruction is lswi, lswx, stswi, stswx, and the core is in little-endian mode. Note
• The operand of dcbz is in memory that is write-through-required or caching-inhibited.
• FPSCR[FEX] is set by the execution of a floating-point instruction that causes an
• Illegal instruction—An illegal instruction program interrupt is generated when execution
• Privileged instruction—A privileged instruction program interrupt is generated when the
• Trap—A trap type program interrupt is generated when any of the conditions specified
that PowerPC little-endian mode is not supported on the e300 core.
enabled exception or by the execution of one of the Move to FPSCR instructions that
results in both an exception condition bit and its corresponding enable bit being set in
the FPSCR.
of an instruction is attempted with an illegal opcode or illegal combination of opcode and
extended opcode fields (including PowerPC instructions not implemented in the core),
or when execution of an optional instruction not provided in the core is attempted (these
do not include those optional instructions that are treated as no-ops).
execution of a privileged instruction is attempted and the MSR register user privilege
bit, MSR[PR], is set. In the e300 core, this interrupt is generated for mtspr or mfspr with
an invalid SPR field if SPR[0] = 1 and MSR[PR] = 1. This may not be true for all cores
that implement the PowerPC architecture.
in a trap instruction are met.
(MSR[FE0] | MSR[FE1]) and FPSCR[FEX] is 1.
Exception Conditions
—
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