MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 613

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

13.3.2.19 Endpoint Flush Register (ENDPTFLUSH)—Non-EHCI
The endpoint flush register, shown in
is only used in device mode.
Table 13-28
13.3.2.20 Endpoint Status Register (ENDPTSTATUS)—Non-EHCI
The endpoint status register, shown in
is only used in device mode.
Freescale Semiconductor
Offset 0x1B4
Reset
Offset 0x1B8
Reset
31–19
18–16 FETB Flush endpoint transmit buffer. Writing a one to a bit(s) in this register will cause the associated endpoint(s) to
15–3
Bits
2–0
W
W
R
R
31
31
Name
FERB Flush endpoint receive buffer. Writing a one to a bit(s) will cause the associated endpoint(s) to clear any primed
—
—
describes the endpoint flush register fields.
Reserved, should be cleared.
clear any primed buffers. If a packet is in progress for one of the associated endpoints, then that transfer will
continue until completion. Hardware will clear this register after the endpoint flush operation is successful.
FETB[2] (bit 18 of the register) corresponds to endpoint 2.
Reserved, should be cleared.
buffers. If a packet is in progress for one of the associated endpoints, then that transfer will continue until
completion. Hardware will clear this register after the endpoint flush operation is successful. FERB[2]
corresponds to endpoint 2.
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
—
—
Table 13-28. ENDPTFLUSH Register Field Descriptions
Figure 13-26. Endpoint Status (ENDPTSTATUS)
Figure 13-25. Endpoint Flush (ENDPTFLUSH)
21
Figure
Figure
19 18
13-25, is not defined in the EHCI specification. This register
18
13-25, is not defined in the EHCI specification. This register
FETB
ETBR
16 15
16 15
All zeros
All zeros
Description
—
—
Universal Serial Bus Interface
Access: Read/Write
Access: Read only
3
3
2
2
FERB
ERBR
13-35
0
0