MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 641

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

13.5.6.2
The second and third DWords of a queue head specify static information about the endpoint. This
information does not change over the lifetime of the endpoint. There are three types of information in this
region:
The host controller must not modify the bits in this region.
Table 13-58
Freescale Semiconductor
31–28
26–16
Bits
Bits
2–1
27
15
0
•
•
•
Endpoint characteristics. These are the USB endpoint characteristics, which include addressing,
maximum packet size, and endpoint speed.
Endpoint capabilities. These are adjustable parameters of the endpoint. They affect how the
endpoint data stream is managed by the host controller.
Split transaction characteristics. This data structure manages full- and low-speed data streams for
bulk, control, and interrupt with split transactions to USB 2.0 Hub transaction translator.
Additional fields exist for addressing the hub and scheduling the protocol transactions (for
periodic).
Name
Packet Length
Typ
T
Maximum
Name
and
Endpoint Capabilities/Characteristics
RL
C
H
Indicates to the hardware whether the item referenced by the link pointer is an iTD, siTD or a QH. This allows
the host controller to perform the proper type of processing on the item after it is fetched.
00 iTD (isochronous transfer descriptor)
01 QH (queue head)
10 siTD (split transaction isochronous transfer descriptor)
11 FSTN (frame span traversal node)
Terminate.
1 Last QH (pointer is invalid).
0 Pointer is valid.
If the queue head is in the context of the periodic list, a one bit in this field indicates to the host controller that
this is the end of the periodic list. This bit is ignored by the host controller when the queue head is in the
asynchronous schedule. Software must ensure that queue heads reachable by the host controller always
have valid horizontal link pointers.
Table 13-59
Table 13-58. Endpoint Characteristics: Queue Head DWord 1
Nak count reload. This field contains a value, which is used by the host controller to reload the Nak
Counter field.
Control endpoint flag. If the QH[EPS] field indicates the endpoint is not a high-speed device, and the
endpoint is a control endpoint, then software must set this bit to a one. Otherwise, it should always
set this bit to a zero.
This directly corresponds to the maximum packet size of the associated endpoint
(wMaxPacketSize). The maximum value this field may contain is 0x400 (1024).
Head of reclamation list flag. This bit is set by system software to mark a queue head as being the
head of the reclamation list.
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
describe the endpoint characteristics.
Table 13-57. Queue Head DWord 0 (continued)
Description
Description
Universal Serial Bus Interface
13-63