MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 292

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Integrated Programmable Interrupt Controller (IPIC)
Table 8-16
8.5.9
SICNR, shown in
SYSA0–SYSA1, SYSB0–SYSB1, SYSC0–SYSC1, and SYSD0–SYSD1 priority positions. All other
priority positions assert int to the core.
Note that in core disabled mode the user should use the int output interrupt type (should not use cint or smi
output interrupt types) to read an updated SIVCR.
Table 8-17
8-18
0–31
Bits Name
Offset 0x28
Reset
Bits
0–1
2–3
4–7
W
R
INT n Each implemented bit (listed in
SYSD0T SYSD1T
SYSD0T SYSD0 priority position IPIC output interrupt type. Defines which type of the IPIC output interrupt signal ( int ,
SYSD1T Same as SYSD0T, but for SYSD1T.
0
Name
—
defines the bit fields of SIMSR_L.
defines the bit fields of SICNR.
System Internal Interrupt Control Register (SICNR)
1
interrupt by clearing the corresponding SIMSR bit. An interrupt is unmasked (enabled) by setting the
corresponding SIMSR bit. The SIMSR can be read by the user at any time.
Note:
Unimplemented bits, shown as reserved in
• SIMSR bit positions are not changed according to their relative priority.
• The user can clear pending register bits that were set by multiple interrupt events only by clearing all unmasked
• If an SIMSR bit is masked at the same time that the corresponding SIPNR bit causes an interrupt request to
events in the corresponding event register.
the core, the error vector is issued (if no other interrupts are pending). Thus, the user should always include
an error
cint , or smi ) asserts its request to the core in the SYSD0 priority position. These bits cannot be changed
dynamically. (to change it, software must make sure the corresponding interrupt source is masked or it cannot
happen during the change).
The definition of SYSD0T is as follows:
00 int request is asserted to the core for SYSD0.
01 smi request is asserted to the core for SYSD0.
10 cint request is asserted to the core for SYSD0.
11 Reserved
Write ignored, read = 0
2
Figure
3
Figure 8-12. System Internal Interrupt Control Register (SICNR)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
4
8-12, defines the IPIC output interrupt type (int, cint, or smi) in the
—
7
SYSC0T SYSC1T
8
Table 8-16. SIMSR_L Field Descriptions
Table 8-17. SICNR Field Descriptions
9
Table
10
8-9) corresponds to an external interrupt source. The user masks an
11
Figure
12
—
All zeros
Description
15
8-11, are ignored on writes; read = 0.
Description
SYSB0T SYSB1T
16
17
18
19
20
—
23
SYSA0T SYSA1T
24
Freescale Semiconductor
25
Access: Read write
26
27
28
—
31