MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 534

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Enhanced Secure Digital Host Controller
11.6.3.2.2
In general, the read operation is not able to pause. Only the SDIO card (and SD Combo card working under
I/O mode) supporting the read wait feature can pause during the read operation. If the SDIO card supports
read wait (CCCR[SRW] = 1), the driver can set PROCTL[SABGREQ] to pause the transfer between the
data blocks. Before setting SABGREQ, PROCTL[RWCTL] must be set. Otherwise, the eSDHC does not
assert the read wait signal during the block gap and data corruption occurs. It is recommended to set the
RWCTL bit once the read wait capability of the SDIO card is recognized.
Similar to the flow described in
same type of read operations:
Similar to the write operation, it is possible to meet the ending block of the transfer when paused. In this
case, the eSDHC ignores the stop-at-block-gap request and treats it as a command read operation.
Unlike the write operation, there is no remaining data inside the buffer when the transfer is paused. All
data received before the pause is transferred to the host system. Whether or not a suspend command is sent,
the internal data buffer is not flushed.
11-54
5. Disable the buffer read ready interrupt, configure the DMA setting, and enable the eSDHC DMA
6. Wait for the transfer complete interrupt.
7. Check the status bit to see if a read CRC error or any other errors occurred between sending Auto
1. Check CCCR[SRW] in the SDIO card to confirm the card supports read wait.
2. Set PROCTL[RWCTL].
3. Check the card status and wait until the card is ready for data.
4. Set the card block length.
5. Set eSDHC BLKATTR[BLKSIZE] to the same as the block length set in the card in Step 2.
6. Set eSDHC BLKATTR[BLKCNT] with the number of blocks to send.
7. Disable the buffer read ready interrupt, configure the DMA setting, and enable the eSDHC DMA
8. Set PROCTL[SABGREQ].
9. Wait for the transfer complete interrupt.
10. Clear PROCTL[SABGREQ].
11. Check the status bit to see if a read CRC error occurred.
12. Set PROCTL[CREQ] to continue the read operation.
13. Wait for the transfer complete interrupt.
14. Check the status bit to see if a read CRC error or any other errors occurred between sending Auto
when sending the command with data transfer. Set XFERTYP[AC12EN].
CMD12 and receiving the response.
— MMC/SD cards — use SET_BLOCKLEN (CMD16)
— SDIO cards or the I/O portion of SD Combo cards — use IO_RW_DIRECT (CMD52) to set
when sending the command with data transfer. Set XFERTYP[AC12EN].
CMD12 and receiving the response.
IO block size bit field in CCCR register (for function 0) or FBR (for functions 1–7)
Read with Pause
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Section 11.6.3.2.1, “Normal Read,”
the read with pause is shown with the
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