MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 174

MPU POWERQUICC II PRO 473MAPBGA

MPC8308VMAGD

Manufacturer Part Number
MPC8308VMAGD
Description
MPU POWERQUICC II PRO 473MAPBGA
Manufacturer
Freescale Semiconductor

Specifications of MPC8308VMAGD

Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
400MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
473-MAPBGA
Product
Network Processor
Data Rate
256 bps
Frequency
400 MHz
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Supply Current (max)
5 uA
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
0 C
Interface
I2C, JTAG, SPI
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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System Configuration
5.3.1
The device provides a software watchdog timer (WDT) feature to prevent system lock in case the software
becomes trapped in loops with no controlled exit. Watchdog timer operations are configured in the system
watchdog control register (SWCRR).
The watchdog counter is a free-running down-counter that generates a reset or a non-maskable interrupt
on underflow. To prevent a reset, software must periodically restart the countdown. The WDT is
responsible for asserting a hardware reset or machine-check interrupt (mcp) if the software fails to service
the software watchdog timer for a certain period of time (for example, because software is lost or trapped
in a loop with no controlled exit).
Figure 5-21
The software watchdog timer is enabled after reset to cause a hardware reset if it times out. The user has
the option of disabling the software watchdog if it is not needed. If used, the software watchdog timer
requires a special service sequence to be executed periodically. Without this periodic servicing, the
software watchdog timer times out and issues a reset or a non-maskable interrupt.
5.3.2
The WDT includes the following key features:
5.3.3
The WDT unit can operate in the following modes:
5-32
Based on 16-bit prescaler and 16-bit down-counter
Provides a selectable range for the time-out period
Provides ~34.36 sec maximum software time-out delay for 125-MHz input clock
Functional and programming compatibility with MPC8260 watchdog timer
WDT enable/disable mode
If the software watchdog timer is not needed, the user can disable it with software after a system
reset. When the watchdog timer is disabled, the watchdog counter and prescaler counter are held
in a stopped state.
WDT output reset/interrupt mode
WDT Overview
WDT Features
WDT Modes of Operation
shows a high-level block diagram of the WDT.
Figure 5-21. Software Watchdog Timer High-Level Block Diagram
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
System
clock
Register Interface
Watchdog
Software
Timer
or mcp
Reset
Freescale Semiconductor

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