MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 236
MPC8308VMAGD
Manufacturer Part Number
MPC8308VMAGD
Description
MPU POWERQUICC II PRO 473MAPBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8308VMAGD.pdf
(90 pages)
2.MPC8308VMAGD.pdf
(2 pages)
3.MPC8308VMAGD.pdf
(1170 pages)
4.MPC8308VMAGD.pdf
(14 pages)
Specifications of MPC8308VMAGD
Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
400MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
473-MAPBGA
Product
Network Processor
Data Rate
256 bps
Frequency
400 MHz
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Supply Current (max)
5 uA
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
0 C
Interface
I2C, JTAG, SPI
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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e300 Processor Core Overview
7-4
•
•
•
Independent execution units and two register files
— Branch processing unit (BPU) featuring static branch prediction
— Two 32-bit integer units (IU) in the e300c3
— FPU based on the IEEE Std 754™ for both single- and double-precision operations
— Load/store unit (LSU) for data transfer between data-cache and general-purpose registers
— System register unit (SRU) that executes condition register (CR), special-purpose register
— Thirty-two 32-bit GPRs for integer operands
— Thirty-two 64-bit FPRs for single- or double-precision operands
High instruction and data throughput
— Zero-cycle branch capability (branch folding)
— Programmable static branch prediction on unresolved conditional branches
— Two integer units with enhanced multipliers in the e300c3 for increased integer instruction
— Instruction fetch unit capable of fetching two instructions per clock from the instruction cache
— A six-entry instruction queue (IQ) that provides lookahead capability
— Independent pipelines with feed-forwarding that reduces data dependencies in hardware
— 16-Kbyte, four-way set-associative instruction and data caches on the e300c3
— Cache write-back or write-through operation programmable on a per-page or per-block basis
— Features for instruction and data cache locking and protection
— BPU that performs CR lookahead operations
— Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte
— A 64-entry, two-way, set-associative ITLB and DTLB
— Eight-entry data and instruction BAT arrays providing 128-Kbyte to 256-Mbyte blocks
— Software table search operations and updates supported through fast trap mechanism
— 52-bit virtual address; 32-bit physical address
Facilities for enhanced system performance
— A 64-bit split-transaction internal data bus interface to the coherent system bus (CSB) with
— Support for one-level address pipelining on the CSB interface
— True little-endian mode for compatibility with other true little-endian devices
— Critical interrupt support
— Hardware support for misaligned little-endian accesses
— Configurable processor bus frequency multipliers as defined in the PowerQUICC II Pro
(GPRs) and floating-point registers (FPRs)
(SPR), and integer add/compare instructions. Add/compare instructions are also executed in
the IUs.
throughput and a maximum two-cycle latency for multiply instructions
segment size
burst transfers
MPC8308 Hardware Specification
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Freescale Semiconductor
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