MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 490

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Enhanced Secure Digital Host Controller
Table 11-7
11-10
14–15
16–25
Bit
26
27
28
29
30
31
Multi/Single Block Select
XFERTYP[MSBSEL]
shows how register settings determine types of data transfers.
RSPTYP
MSBSEL
DTDSEL
AC12EN
DMAEN
Name
BCEN
—
—
0
1
1
1
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Response type select.
00 No response
01 Response length 136
10 Response length 48
11 Response length 48 check busy after response
Reserved
Multi/single block select. Enables multiple block SD_DAT line data transfers. For any other
commands, this bit should be cleared. If this bit is cleared, it is not necessary to set the block
count register. (Refer to
0 Single block
1 Multiple blocks
Data transfer direction select. Defines the direction of SD_DAT line data transfers. The bit is set
by the host driver to transfer data from the SD card to the eSDHC and it is cleared for all other
commands.
0 Write (host to card)
1 Read (card to host)
Reserved
Auto CMD12 enable. Multiple block transfers for memory require CMD12 to stop the transaction.
If this bit is set, the eSDHC issues CMD12 automatically when the last block transfer is
completed. The host driver should not set this bit to issue commands that do not require CMD12
to stop a multiple block data transfer. In particular, secure commands defined in the Part 3 File
Security specification do not require CMD12. In a single block transfer, the eSDHC ignores this
bit.
0 Disable
1 Enable
Block count enable. Enables the block attributes register, which is only relevant for multiple block
transfers. When this bit is cleared, the block attributes register is disabled, which is useful in
executing an infinite transfer.
0 Disable
1 Enable
DMA enable. Enables DMA functionality as described in
If this bit is set, a DMA operation should begin when the host driver writes to the CMDINX field
of the transfer type register.
0 Disable
1 Enable
Table 11-6. XFERTYP Field Descriptions (continued)
Table 11-7. Determination of Transfer Type
Block Count Enable
XFERTYP[BCEN]
Don’t Care
0
1
1
Table
11-7.)
BLKATTR[BLKCNT]
Positive Number
Block Count
Don’t Care
Don’t Care
Description
Zero
Section 11.5.2, “DMA CSB Interface.”
No Data Transfer
Multiple Transfer
Infinite Transfer
Single Transfer
Function
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