MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 938

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
Table 16-32
16.5.3.3.7
RQFCR is accessed to read or write the RQCTRL words in entries of the receive queue filer table. The
table entries are described in greater detail in
through RQFCR is defined by the current value of RQFAR.
Figure 16-28
Table 16-33
16-54
Offset eTSEC1:0x2_4338; eTSEC2:0x2_5338
Reset
24–31
16–21
0–23
1–15
Bits
Bit
Offset eTSEC1:0x2_4334; eTSEC2:0x2_5334
0
Reset
W
R
W
GPI
R
0
Name
RQFAR Current index of receive queue filer table, which spans a total of 256 entries.
Name
0
GPI
—
Q
—
1
describes the fields of the RQFAR register.
describes the fields of the RQFCR register.
describes the definition for the RQFCR register.
Receive Queue Filer Table Control Register (RQFCR)
General purpose interrupt. When a property matches the value in the RQPROP entry at this index, and
REJ = 0 and AND = 0, the filer will instruct the Rx descriptor controller to set IEVENT[FGPI] when the
corresponding receive frame is written to memory.
If the timer is enabled (TMR_CTRL[TE] = 1), then TMR_PEVENT[RXP] will also be set.
Reserved, should be written with zero.
Receive queue index, from 0 to 63, inclusive, written into the Rx frame control block associated with the
received frame. When a property matches the value in the RQPROP entry at this index, and REJ = 0 and
AND = 0, the frame is sent to either RxBD ring 0 (if RCTRL[FSQEN] = 1) or the RxBD ring with index (Q mod
8) and the filing table search is terminated. In the case where RCTRL[FSQEN] = 0, 8 virtual receive queues
are overlaid on every RxBD ring, and software needs to consult the RQ field of the Rx frame control block to
determine which virtual receive queue was chosen.
Reserved
Figure 16-27. Receive Queue Filer Table Address Register Definition
Figure 16-28. Receive Queue Filer Table Control Register Definition
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
—
Table 16-33. RQFCR Field Descriptions
Table 16-32. RQFAR Field Descriptions
—
Section 16.6.4.2, “Receive Queue Filer.”
(undefined)
15 16
All zeros
Description
Description
Q
21
CLE REJ AND CMP —
22
23
23 24
24
Freescale Semiconductor
25 26 27 28
The word accessed
Access: Read/Write
Access: Read/Write
RQFAR
PID
31
31