MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 951

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
Bits
26
27
28
29
30
31
PAD/CRC
CRC EN
Length
Duplex
Frame
Name
check
Huge
Full
—
Huge frame enable. This bit is cleared by default.
0 Limit the length of frames received to less than or equal to the maximum frame length value
1 Frames are transmitted and received regardless of their relationship to the maximum frame length.
Note that if Huge Frame is cleared, the user must ensure that adequate buffer space is allocated for
Length check. This bit is cleared by default.
0 No length field checking is performed.
1 The MAC checks the frame’s length field on receive to ensure it matches the actual data field length.
Reserved
(MACCFG2[Full Duplex] is cleared).
0 Frames presented to the MAC have a valid length and contain a CRC.
1 The MAC pads all transmitted short frames and appends a CRC to every frame regardless of
CRC enable. If the configuration bit PAD/CRC ENABLE or the per-packet PAD/CRC ENABLE is set,
CRC ENABLE is ignored. This bit is cleared by default.
0 Frames presented to the MAC have a valid length and contain a valid CRC.
1 The MAC appends a CRC on all frames. Clear this bit if frames presented to the MAC have a valid
Full duplex configure. This bit is cleared by default.
0 The MAC operates in half-duplex mode only.
1 The MAC operates in full-duplex mode.
Pad and append CRC. This bit is cleared by default. This bit must be set when in half-duplex mode
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
(MAXFRM[Maximum Frame]) and limit the length of frames transmitted to less than the maximum
frame length.
See
received frames. See
information.
Transmitted frames are not checked.
padding requirement.
length and contain a valid CRC.
Receive or transmit > maximum frame length
Receive
Transmit
Receive or transmit < maximum frame length
Table 16-40. MACCFG2 Field Descriptions (continued)
Section 16.6.7, “Buffer
Frame type
Section 16.5.3.5.5, “Maximum Frame Length Register
= maximum frame length
= maximum frame length
Descriptors,” for further details of buffer descriptor bit updating.
Frame length
Description
Enhanced Three-Speed Ethernet Controllers
truncation
Packet
yes
no
no
no
Buffer descriptor
(MAXFRM),” for further
updated
yes
yes
no
no
16-67