MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 208

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

System Configuration
triggering the capture is selected by the corresponding GTMDRn[CE] bits. Upon a capture or reference
event, corresponding GTEVRn[REF] or GTEVRn[CAP] is set and a maskable interrupt request is issued
to the interrupt controller.
The gate function is enabled in the GTMDR; the gate operating mode is selected in the GTCFRn.
5.6.6.4
GTCFRn[PCAS] and GTCFR2[SCAS] are used to put the timers into different cascaded modes:
5-66
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•
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Normal gate mode enables the count on a falling edge of TGATE and disables the count on the
rising edge of TGATE. This mode allows the timer to count conditionally, based on the state of
TGATE.
The restart gate mode performs the same function as normal mode, except it also resets the counter
on the falling edge of TGATE.
This mode has applications in pulse interval measurement and bus monitoring as follows:
— Pulse measurement—The restart gate mode can measure a low pulse on TGATE. The rising
— Bus monitoring—The restart gate mode can detect a signal that is stuck abnormally low. The
Non-cascaded mode (GTCFRn[PCAS] = 0 and GTGCF2[SCAS] = 0)
If GTCFRn[PCAS] = 0 and GTCFR2[SCAS] = 0, each timer (timer 1, timer 2, timer 3, and timer
4), function as a independent 16-bit timer with a 16-bit GTRFR, GTCPR, GTMDR, and GTCNR
for each one
GTCPR, and GTCNR should be referenced with appropriate 16-bit bus cycles.
Pair-cascaded mode (GTCFR1[PCAS] = 1 and/or GTCFR2[PCAS] = 1, GTCFR2[SCAS] = 0)
edge of TGATE completes the measurement and if TGATEn is connected externally to TINn,
it causes the timer to capture the count value and generate a rising-edge interrupt.
bus signal should be connected to TGATE. The timer count is reset on the falling edge of the
bus signal and if the bus signal does not go high again within the number of user-defined
clocks, an interrupt can be generated.
GTRFR1, GTCPR1, GTCNR1
GTRFR3, GTCPR3, GTCNR3
Cascaded Modes
TGATE is internally synchronized to the system clock. If TGATE meets the
asynchronous input setup time, the counter begins or stops counting after
one system clock when working with the internal clock.
(Figure
Timer1
Timer3
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Figure 5-51. Timers Non-Cascaded Mode Block Diagram
5-51). When working in the none-cascaded mode, the non-cascaded GTRFR,
Capture
Capture
Clock
Clock
NOTE
GTRFR2, GTCPR2, GTCNR2
GTRFR4, GTCPR4, GTCNR4
Timer2
Timer4
Capture
Capture
Freescale Semiconductor
Clock
Clock