MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 929

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16.5.3.2.9
The TBASEn registers are written by the user with the base address of each TxBD ring n. Each such value
must be divisible by eight, since the three least significant bits always write as 000.
the definition for the TBASEn registers.
Table 16-24
16.5.3.2.10 Transmit Time Stamp Identification Register (TMR_TXTS1–2_ID)
Transmit time stamp identification register (TMR_TXTSn_ID). This register holds the identification
number of the transmitted frame corresponding to the timestamp captured in TMR_TXTSn_H/L. Each
time the eTSEC is instructed to capture the timestamp of an outgoing frame via TxFCB[PTP] the
associated field in TxFCB[PTP_ID] is stored in this register, overwriting the previous value.
This register is read only in normal operation.
TMR_TXTSn_ID register.
Table 16-25
Freescale Semiconductor
Offset eTSEC1:0x2_4280+4×n; eTSEC2:0x2_5280+4×n
29–31
Reset
0–28 TBASE n Transmit base for ring n . TBASE defines the starting location in the memory map for the eTSEC TxBDs. This
16–31
Bits
0–15
Bits
Offset eTSEC1:0x2_4204+8× n ; eTSEC2:0x2_5204+8× n
Reset
W
R
W
R
0
Name
—
0
TXTS_ID
Name
describes the fields of the TBASEn registers.
describes the fields of the TMR_TXTSn_ID register.
—
field must be 8-byte aligned. Together with setting the W (wrap) bit in the last BD, the user can select how many
BDs to allocate for the transmit packets. The user must initialize TBASE before enabling the eTSEC transmit
function on the associated ring.
Reserved
Transmit Descriptor Base Address Registers (TBASE0–TBASE7)
Reserved
Tx time stamp identification field
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Table 16-25. TMR_TXTS n _ID Register Field Descriptions
Table 16-24. TBASE0–TBASE7 Field Descriptions
Figure 16-20. TMR_TXTS n _ID Register Definition
—
Figure 16-19. TBASE Register Definition
Figure 16-20
TBASE n
All zeros
All zeros
15 16
Description
Description
describes the definition for the
Enhanced Three-Speed Ethernet Controllers
TXTS_ID
Figure 16-19
Access: Read/Write
Access: Read only
28 29
describes
—
16-45
31
31