MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 338

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DDR Memory Controller
Table 9-12
9-20
11–12
Bits
5–7
8–9
10
13
14
15
16
0
1
2
3
4
SDRAM_TYPE
DYN_PWR
MEM_EN
ECC_EN
RD_EN
describes the DDR_SDRAM_CFG fields.
2T_EN
Name
SREN
NCAP
DBW
—
—
—
—
DDR SDRAM interface logic enable.
0 SDRAM interface logic is disabled.
1 SDRAM interface logic is enabled. Must not be set until all other memory configuration
Self refresh enable (during sleep).
0 SDRAM self refresh is disabled during sleep. Whenever self-refresh is disabled, the system is
1 SDRAM self refresh is enabled during sleep.
ECC enable. Note that uncorrectable read errors may cause an interrupt.
0 No ECC errors are reported. No ECC interrupts are generated.
1 ECC is enabled.
Registered DRAM module enable. Specifies the type of DRAM module used in the system.
0 Indicates unbuffered DRAM modules.
1 Indicates registered DRAM modules.
Note: RD_EN and 2T_EN must not both be set at the same time.
Reserved
Type of SDRAM device to be used. This field is used when issuing the automatic hardware
initialization sequence to DRAM through Mode Register Set and Extended Mode Register Set
commands.
For DDR2 SDRAM, the field is set to 011.
Reserved
Dynamic power management mode
0 Dynamic power management mode is disabled.
1 Dynamic power management mode is enabled. If there is no ongoing memory activity, the
DRAM data bus width.
00
01
10
11
Reserved
Non-concurrent auto-precharge. Some older DDR DRAMs do not support concurrent auto
precharge. If one of these devices is used, then this bit needs to be set if auto precharge is used.
0 DRAMs in system support concurrent auto-precharge.
1 DRAMs in system do not support concurrent auto-precharge.
Reserved
Enable 2T timing.
0 1T timing is enabled. The DRAM command/address are held for only 1 cycle on the DRAM bus.
1 2T timing is enabled. The DRAM command/address are held for 2 full cycles on the DRAM bus
Note: RD_EN and 2T_EN must not both be set at the same time.
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
parameters have been appropriately configured by initialization code.
responsible for preserving the integrity of SDRAM during sleep.
SDRAM CKE signal is negated.
for every DRAM transaction. However, the chip select is only held for the second cycle.
Reserved
32-bit bus is used
16-bit bus is used
Reserved
Table 9-12. DDR_SDRAM_CFG Field Descriptions
Description
Freescale Semiconductor