MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 844

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PCI Express Interface Controller
PEX_OWTARLn and PEX_OWTARHn registers. This register should be used in 64-bit addressing.
Otherwise it should contain all zeroes.
Table 14-129
14.5.11 PCI Express EP Inbound Address Translation Registers
The following registers are used as the base address for the CSB domain to translate the address of an
inbound transaction from the PCI Express domain. They are valid only in End Point (EP) mode and operate
in conjunction with the base address registers in the PCI Express configuration space.
When a PCI Express inbound transaction hits a valid address window defined by the PCI Express
configuration space base address registers and the respective translation register is enabled, the incoming
address is translated to a CSB domain address and the transaction is forwarded to the CSB.
The correspondence between the PCI Express configuration space base address registers and the
respective translation address registers is shown in
14-106
Offset 0xCAC, 0xCBC, 0xCCC, 0xCDC
Reset
(Configuration Space)
31–0
Bits
W
R
Base Address
31
Register
0x01C
Name
0x010
0x014
0x018
0x020
0x024
TAH
Table 14-130. EP Inbound Base and Translation Address Registers Correspondence
Figure 14-131. PCI Express Outbound Window Translation Address Register High n
defines the bit fields of PEX_OWTARHn.
Translation address high. Higher portion of the PCI Express address base ([63–32]). The complete 64-bit
address on the PCI Express bus is built of {PEX_OWTARH[TAH],PEX_OWTARL[TAL], 0x000}.
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
BAR Name
Table 14-129. PEX_OWTARH n Register Fields Description
BAR0
BAR1
BAR2
BAR3
BAR4
BAR5
(PEX_OWTARH0–PEX_OWTARH3)
Window 0, 32-bit address
Window 1, 32-bit address
Window 2, 64-bit address, low portion
Window 2, 64-bit address, high portion
Window 3, 64-bit address, low portion
Window 3, 64-bit address, high portion
Table
Type
All zeros
TAH
Description
14-130.
TAR Address
0xDEC
0xDE0
0xDE4
0xDE8
Freescale Semiconductor
Access: Read/Write
PEX_EPIWTAR0
PEX_EPIWTAR1
PEX_EPIWTAR2
PEX_EPIWTAR3
TAR Name
0