MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 169

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 5-28
5.2.2.10
Figure 5-17
Freescale Semiconductor
Offset 0x0012C
Reset 0
10–11
14–28
Bits
2–5
6–9
12
13
29
30
31
0
1
W
R
0
MVREF_SEL MVREF_SEL
—
DDR_TYPE
DSO_EN
DSO_NZ
DSO_PZ
0 1 1 0 0 1
1
shows the bit definition of the DDRCDR.
M_odr
Name
ODT
contains the debug status bits from the DDR SDRAM controller.
—
—
—
—
DDR Debug Status Register (DDRDSR)
2
PZ
5
Reserved
0 DDR driver software override disable
1 DDR driver software override enable
DDR driver software p-impedance override
0000 Half strength—Highest Z
1000 Much higher Z than nominal
1100 Higher Z than nominal
1110 Nominal impedance setting
1111 Lower Z than nominal
DDR driver software n-impedance override
0000 Half strength—Highest Z
1000 Much higher Z than nominal
1100 Higher Z than nominal
1110 Nominal impedance setting
1111 Lower Z than nominal
Reserved. Should be cleared.
ODT termination value for I/Os
0 75 Ω
1 150 Ω
Selects voltage level for DDR pads
0 DDR2 (1.8V mode) nominal impedance—18 Ω
1 DDR1 (2.5V mode) nominal impedance—18 Ω
Note: DDR_TYPE must be set according to the logical type of the DDR memory devices, as it affects
Reserved
0 MVREF is i/p from external source
1 MVREF is generated internally from GVDD
Disable memory transaction reordering
0 Memory transaction reordering enabled
1 Memory transaction reordering disabled
Reserved
6
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
1
logic behavior of the DDR controller as well as the physical parameters of the DDR I/O pads.
NZ
Figure 5-17. DDR Debug Status Register (DDRDSR)
0
0
9
Table 5-28. DDRCDR Field Descriptions
10
0
0
0
0
0
0
0
Description
0
0
0
0
—
0
0
0
0
0
0
System Configuration
0
Access: Read
0
0
0
5-27
31
0