MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 515

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

11.4.15 Watermark Level Register (WML)
Figure 11-17
The value can be any number from 1–127 words.
Table 11-23
11.4.16 Force Event Register (FEVT)
The force event register is not a physically implemented register. Rather, it is an address to which the
IRQSTAT register can be written if the corresponding bit of IRQSTATEN is set. Therefore, this register is
a write-only register and writing zero has no effect. Writing 1 to this register sets the corresponding bit of
IRQSTAT. Reading from this register always returns zeroes.
Forcing a card interrupt generates a short pulse on the SD_DAT[1] line, and the driver may treat this
interrupt as normal. The interrupt service routine may skip polling the card-interrupt source as the interrupt
is self-cleared.
Freescale Semiconductor
Reset
Offset: 0x044 (WML)
13–15
16–31
16–23
24–31
Bit
8–15
W
0–7
Bit
R
0
0
describes the WML fields.
0
shows the watermark level register. Both write and read watermark levels are configurable.
0
Name
MBL
1
—
WR_WML
RD_WML
—
Name
0
—
—
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Table 11-22. HOSTCAPBLT Field Descriptions (continued)
0
Max block length. Indicates the maximum block size that the host driver can read and write to
the buffer in the eSDHC. The buffer should transfer block size without wait cycles.
000 512 bytes
001 1024 bytes
010 2048 bytes
011 4096 bytes
Reserved
0
Figure 11-17. Watermark Level Register (WML)
0
7
Reserved.
Write watermark level. Number of 32-bit words of watermark level in write data transfer.
Note: The minimum value is 0x02, which represents 2 words (8 bytes).
Reserved.
Read watermark level. Number of 32-bit words of watermark level in read data transfer.
0
8
Table 11-23. WML Field Descriptions
0
0
WR_WML
1
0
0
0
15 16
0
0
Description
0
Description
0
1
—
0
Enhanced Secure Digital Host Controller
0
0
23 24
0
0
0
Access: Read/Write
0
RD_WML
1
0
0
0
11-35
31
0