MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 890

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
Each eTSEC network interface supports multiple options:
Table 16-1
16-6
TSEC n _GTX_CLK125 Oscillator source for RGMII transmit clock, input, shared by all eTSECs
TSEC_TMR_TRIG1
TSEC_TMR_GCLK
TSEC n _GTX_CLK
TSEC_TMR_CLK
TSEC n _RXD[3:0]
TSEC n _TXD[3:0]
TSEC n _RX_CLK
TSEC n _TX_CLK
•
•
•
TSEC n _RX_ER
TSEC n _RX_DV
TSEC n _TX_ER
TSEC n _TX_EN
Signal Name
TSEC n _COL
TSEC n _CRS
TSEC_MDIO
TSEC_MDC
The MII option requires 18 I/O signals (including the MDIO and MDC MII management interface)
and supports both a data and a management interface to the PHY (transceiver) device. The MII
option supports both 10- and 100-Mbps Ethernet rates.
The RGMII option is reduced-pin implementations of the GMII.
1588 timer signals.
lists the network interface signals.
MII—collision, input
MII—carrier sense, input
RGMII—inverted transmit clock feedback, output
MII—transmit clock feedback when transmission is enabled, zero otherwise, output
Management clock, output.
Management data, bidirectional.
MII, RGMII—receive clock, input
MII—receive data valid, input
RGMII (RX_CLK rising)—receive data valid, input
RGMII (RX_CLK falling)—receive error, input
MII—Receive data bits 3:0, input
RGMII (RX_CLK rising) —Receive data bits 3:0, input
RGMII (RX_CLK falling)—Receive data bits 7:4, input
MII—Receive error, input
RGMII—Unused
MII—transmit clock, input
RGMII—unused
MII—Transmit data bits 3:0, output
RGMII (TX_CLK rising)—Transmit data bits 3:0, output
RGMII (TX_CLK falling)—Transmit data bits 7:4, output
MII—transmit error, output
RGMII—unused, output driven zero
MII—Transmit data valid, output
RGMII (TX_CLK rising)—Transmit data enabled, output
RGMII (TX_CLK falling)—Transmit error, output
1588—Clock input
External high precision timer reference clock input (chip external input pin).
1588—Clock output
Phase aligned timer clock divider output (chip external output pin).
1588—Trigger in 1
External timer trigger input 1. This is an asynchronous general purpose input (chip external
input pin).
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Table 16-1. eTSEC n Network Interface Signal Properties
Function
Freescale Semiconductor
(input)
Reset
State
0000
Hi-Z
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0