MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 765

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

14.4.3
The type 1 header is shown in
Section 14.4.1, “Common PCI Express-Compatible Configuration Header
registers in the first 16 bytes of the header. This section describes the registers that are unique to the type
1 header beginning at offset 0x010.
14.4.3.1
The primary bus number register is shown in
Table 14-22
Freescale Semiconductor
Offset
Reset
Bits
7–0
Reserved
Secondary Latency Timer
W
R
0x018
Bus Number
Primary
Name
Type 1 PCI-Compatible Configuration Header Registers
Figure 14-22. PCI Express PCI Express-Compatible Configuration Header—Type 1
describes the primary bus number register fields.
BIST
7
PCI Express Primary Bus Number Register (RC Mode Only)
Prefetchable Memory Limit
Table 14-22. PCI Express Primary Bus Number Register Fields Description
I/O Limit Upper 16 Bits
Secondary Status
Bridge Control
Memory Limit
Bus that is connected to the upstream interface. Note that this register is programmed during system
enumeration; in RC mode this register should remain 0x00.
Device ID
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Status
Figure 14-23. PCI Express Primary Bus Number Register
Subordinate Bus Number
Figure
Header Type
Class Code
Prefetchable Base Upper 32 Bits
Prefetchable Limit Upper 32 Bits
Expansion ROM Base Address
14-22.
Figure
Primary Bus Number
Secondary Bus Number
All zeros
14-23.
Latency Timer
Interrupt Pin
Description
I/O Limit
Prefetchable Memory Base
I/O Base Upper 16 Bits
Memory Base
Command
Vendor ID
Registers,” describes the
Primary Bus Number
Capabilities Pointer
PCI Express Interface Controller
Cache Line Size
Interrupt Line
Revision ID
I/O Base
Access: Read/Write
Offset (Hex)
Address
0
00
04
08
0C
10
14
18
1C
20
24
28
2C
30
34
38
3C
14-27