MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 711

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

13.8.2.2
This section discusses the suspend and resume functions.
13.8.2.2.1
In order to conserve power, USB_DR automatically enters the suspended state when no bus traffic has
been observed for a specified period. When suspended, the USB_DR maintains any internal status,
including its address and configuration. Attached devices must be prepared to suspend at any time they are
powered, regardless of if they have been assigned a non-default address, are configured, or neither. Bus
activity may cease due to the host entering a suspend mode of its own. In addition, a USB device shall also
enter the suspended state when the hub port it is attached to is disabled.
The USB_DR exits suspend mode when there is bus activity. It may also request the host to exit suspend
mode or selective suspend using electrical signaling to indicate remote wake-up. The ability of a device to
signal remote wake-up is optional. The USB_DR is capable of remote wake-up signaling. When the
USB_DR is reset, remote wake-up signaling must be disabled.
13.8.2.2.2
The USB_DR moves into the suspend state when suspend signaling is detected or activity is missing on
the upstream port for more than a specific period. After the device controller enters the suspend state, the
DCD is notified by an interrupt (assuming DC Suspend Interrupt is enabled). When the USBSTS[SLI]
(device controller suspend) is set, the device controller is suspended.
DCD response when the device controller is suspended is application specific and may involve switching
to low power operation. Information on the bus power limits in suspend state can be found in USB 2.0
specification.
13.8.2.2.3
If the USB_DR is suspended, its operation is resumed when any non-idle signaling is received on its
upstream facing port. In addition, the USB_DR can signal the system to resume operation by forcing
resume signaling to the upstream port. Resume signaling is sent upstream by writing a ‘1’ to the
PORTSC[FPR] (resume bit) while the device is in suspend state. Sending resume signal to an upstream
port should cause the host to issue resume signaling and bring the suspended bus segment (one more
devices) back to the active condition.
13.8.3
The USB 2.0 specification defines an endpoint, also called a device endpoint or an address endpoint as a
uniquely addressable portion of a USB device that can source or sink data in a communications channel
Freescale Semiconductor
Managing Endpoints
Suspend/Resume
Suspend Description
Suspend Operational Model
Resume
Before resume signaling can be used, the host must enable it using the Set
Feature command defined in device framework (Chapter 9) of the USB 2.0
Specification.
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
NOTE
Universal Serial Bus Interface
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