MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 731

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

13.9.1.5.3
The following Universal Serial Bus Revision 2.0 Specification items are implemented in the embedded
transaction translator:
13.9.1.5.4
The following Universal Serial Bus Revision 2.0 Specification items are implemented in the embedded
transaction translator:
13.9.1.5.5
The maximum number of embedded transaction translators that is currently supported is one as indicated
by the N_TT field in the HCSPARAMS register. See
Parameters (HCSPARAMS),”
13.9.2
The co-existence of a device operational controller within the DR module has little effect on EHCI
compatibility for host operation except as noted in this section.
Freescale Semiconductor
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USB 2.0–11.17.3
— Sequencing is provided and a packet length estimator ensures no full-speed/low-speed packet
USB 2.0–11.17.4
— Transaction tracking for 2 data pipes.
USB 2.0–11.17.5
— Clear_TT_Buffer capability provided
USB 2.0–11.18.6.[1-2]
— Abort of pending start-splits
— Abort of pending complete-splits
babbles into SOF time.
– EOF (and not started in microframes 6)
– Idle for more than 4 microframes
– EOF
– Idle for more than 4 microframes
Device Operation
Periodic Transaction Scheduling and Buffer Management
There is no data schedule mechanism for these transactions other than the
microframe pipeline. The embedded TT assumes the number of packets
scheduled in a frame does not exceed the frame duration (1 msec) or else
undefined behavior may result.
Multiple Transaction Translators
Asynchronous Transaction Scheduling and Buffer Management
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
for more information.
NOTE
Section 13.3.1.3, “Host Controller Structural
Universal Serial Bus Interface
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