MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 581

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

13.2
This section contains detailed descriptions of all the USB dual-role controller signals. Many of the signals
for the PHY interfaces are muxed onto the same pins in order to reduce pin count.
signals, indicating which interface supports each signal.
13.2.1
The ULPI (UTMI low pin count interface) is a reduced pin-count (12 signals) extension of the UTMI+
specification. Pin count is reduced by converting relatively static signals to register bits, and providing a
bidirectional, generic data bus that carries USB and register data. This interface minimizes pin count
requirements for external PHYs.
Freescale Semiconductor
USBDR_NXT
USBDR_DIR
Signal
External Signals
ULPI Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
I/O
I
I
transfer to USB port, it drives USBDR_DIR high to take ownership of the bus. When the PHY
has no data to transfer it drives USBDR_DIR low and monitors the bus for link activity. The PHY
pulls USBDR_DIR high whenever the interface cannot accept data from the link.
to the PHY, USBDR_NXT indicates when the current byte has been accepted by the PHY. The
USB port places the next byte on the data bus in the following clock cycle. When the PHY is
sending data to USB port, USBDR_NXT indicates when a new byte is available for USB port
to consume.
Direction. USBDR_DIR controls the direction of the data bus. When the PHY has data to
Next data. The PHY asserts USBDR_NXT to throttle the data. When USB port is sending data
Meaning
Meaning
Timing Synchronous to PHY_CLK.
Timing Synchronous to PHY_CLK.
State
State
Table 13-2
Table 13-2. ULPI Signal Descriptions
Table 13-1. USB External Signals
USBDR_TXDRXD[0:7]
Asserted—PHY has data to transfer to the link.
Negated—PHY has no data to transfer.
Asserted—PHY is ready to transfer byte.
Negated—PHY is not ready.
USBDR_PWR_FAULT
USBDR_PCTL[0:1]
USBDR_CLK
USBDR_NXT
USBDR_STP
USBDR_DIR
Signal
describes the signals for the ULPI interface.
Description
I/O
I/O
O
O
I
I
I
I
Table 13-1
Universal Serial Bus Interface
describes the
13-3