MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 544

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Enhanced Secure Digital Host Controller
11.7
This section discusses the software restrictions.
11.7.1
The driver should not set INITA bit in System Control register when any of the command line or data lines
is active, so the driver should ensure both CDIHB and CIHB bits are cleared. In order to auto clear the
INITA bit, the SDCLKEN bit must be ‘1’, otherwise no clocks can go out to the card and INITA never
clears.
11.7.2
When polling read or write, once the software begins a buffer read or write, it must access exactly the
number of times as set in the watermark level register, as if a DMA burst occurred.
11.7.3
In order to suspend the data transfer, the software must inform eSDHC that the suspend command is
successfully accepted. To achieve this, after the Suspend command is accepted by the SDIO card, software
must send another normal command marked as suspend command (CMDTYP bits set as ‘01’) to inform
eSDHC that the transfer is suspended.
If software needs resume the suspended transfer, it should read the value in BLKCNT register to save the
remained number of blocks before sending the normal command marked as suspend, otherwise on sending
such ‘suspend’ command, eSDHC regards the current transfer as aborted and change BLKCNT register to
its original value, instead of keeping the remained number of blocks.
11.7.4
When the internal DMA is not enabled and a write transaction is in operation, DATPORT (described in
Section 11.4.6, “Buffer Data Port Register
used to read (or write) data by the CPU if the data will be written (or read) by the eSDHC internal DMA.
11.7.5
For pre-defined multi-block read operation, that is, the number of blocks to read has been defined by
previous CMD23 for MMC, or pre-defined number of blocks in CMD53 for SDIO/SDCombo, or whatever
multi-block read without abort command at card side, soft reset for data is required by eSDHC to drive the
internal state machine to idle mode. Then use reset mechanism. For information on reset mechanism, see
Section 3-10, “Error Recovery” in SD Host Controller Specifications, Ver 2.0 (Jan 2007).
11-64
Software Restrictions
Initialization Active
Software Polling Procedure
Suspend Operation
Data Port Access
Multi-block Read
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
(DATPORT)”) must not be read. DATPORT also must not be
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