MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 298

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Integrated Programmable Interrupt Controller (IPIC)
8.5.15
The bits in the SERSR, shown in
source machine check (mcp) conditions listed in
interrupt controller sets the corresponding SERSR bit.
Table 8-23
SERFR.
8-24
Offset 0x40
Reset
10–11
12–15
16–19
20–31
Bits
8–9
W
R
0
MIXA0T MIXA0 priority position IPIC output interrupt Type. Defines which type of the IPIC output interrupt signal ( int ,
MIXA1T Same as MIXA0T, but for MIXA1T.
Name
EDIx
lists the implemented SERSR bits. Note that these field assignments are valid for SERMR and
—
—
System Error Status Register (SERSR)
cint , or smi ) asserts its request to the core in the MIXA0 priority position. These bits can be changed
dynamically. The definition of MIXA0T is as follows:
00 int request is asserted to the core for MIXA0.
01 smi request is asserted to the core for MIXA0.
10 cint request is asserted to the core for MIXA0.
11 Reserved
Write ignored, read = 0
Each bit defines the edge detect mode for the external IRQ n interrupt signals, determines whether the
corresponding IRQ n signal asserts an interrupt request upon either a high-to-low (high assertion for active
high polarity) change or low assertion (high assertion for active high polarity) on the pin. The corresponding
IRQ n signal asserts an interrupt request as follows:
0 Low assertion (high assertion for active high polarity) on IRQ n generates an interrupt request (level
1 High-to-low (low-to-high for active high polarity) change on IRQ n generates an interrupt request (edge
Write ignored, read = 0
sensitive).
sensitive).
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Table 8-23. SERSR/SERMR/SERFR Bit Assignments
Figure 8-18. System Error Status Register (SERSR)
Table 8-22. SECNR Field Descriptions (continued)
Figure
INT n (Implemented bits are listed in
3–31
8-18, correspond to the external and internal non-maskable error
Bits
1
2
0
Table
All zeros
8-23. When an error interrupt signal is received, the
Description
IRQ0
Field
WDT
SBA
—
1
Table
8-23)
Freescale Semiconductor
Access: Read/write
31