MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 1143

• Manufacturer Part Number: MPC8308VMAGD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8308VMAGD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 400 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: 0 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

A.10 Clock Configuration
A.11 Power Management Controller (PMC)
A.12 General Purpose I/O (GPIO)
Freescale Semiconductor
0x00C–0x0FC Reserved, should be cleared
0x004–0x0FC Reserved
0x028–
Offset
0x01C
0x0FC
Offset
Offset
Offset
0x014
0x018
0x020
0x024
0x000
0x004
0x008
0x000
0x000
0x004
Reset mode register (RMR)
Reset protection register (RPR)
Reset control register (RCR)
Reset control enable register (RCER)
Reserved.
Reserved, should be cleared
System PLL mode register (SPMR)
Output clock control register (OCCR)
System clock control register (SCCR)
Power management controller configuration register (PMCCR)
GPIO direction register (GPDIR)
GPIO open drain register (GPODR)
Table A-11. Power Management Controller (PMC) Registers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Power Management Controller—Block Base Address 0x0_0B00
General Purpose I/O (GPIO)—Block Base Address 0x0_0C00
Table A-9. Reset Configuration Registers (continued)
Table A-12. General Purpose I/O (GPIO) Registers
Clock Configuration—Block Base Address 0x0_0A00
Reset Configuration—Block Base Address 0x0_0900
Table A-10. Clock Configuration Registers
Register
Register
Register
Register
Complete List of Configuration, Control, and Status Registers
Access
Access
Access
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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—
—
—
R
0x0000_0000
0x nnnn _ nnnn
0x0000_E080
0x5550_0010
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
Reset
Reset
Reset
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Section/Page
Section/Page
Section/Page
4.5.1.4/4-27
4.5.1.5/4-28
4.5.1.6/4-28
4.5.1.7/4-29
4.5.2.1/4-30
4.5.2.2/4-31
4.5.2.3/4-32
5.7.2.1/5-69
21.3.1/21-3
21.3.2/21-3
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A-7